Patent Application
20240222474
This application claims priority from French Patent Application No. 2213369 filed on Dec. 14, 2022. The content of this application is incorporated herein by reference in its entirety.
The present application relates to the field of quantum electronic devices with quantum bits (also called qubits or Qbits), formed from regions of semiconductor quantum dots and using, besides “front” control gate electrodes located above the dots, one or more exchange electrodes to allow a coupling between two dots or between a dot and a charge reservoir.
Quantum dots form basic elements of a quantum electronic device. Quantum dots are typically formed in a region of semiconductor material in which potential wells are implemented to confine carriers, electrons or holes, in the three dimensions of space. A piece of quantum information is thus encoded via the spin of the carrier. These are thus called spin qubits.
The quantum devices with spin qubits formed using a semiconductor region have the advantage of allowing a manufacturing of a significant density of qubits and of being able to co-integrate these qubits with other components, for example such as transistors.
According to one approach, electrons are confined by field effect under gate electrodes similar to those of the structures of transistors and the piece of information is encoded in the spin of these electrons. These “front” gates are disposed above the quantum dots.
To allow improved control and be able to carry out a tunnel coupling between neighbouring dots and thus be able to modify a tunnel barrier between these neighbouring quantum dots, additional electrodes, called exchange electrodes, can be provided.
Thus, the document “A Single-Electron Injection Device for CMOS Charge Qubits Implemented in 22-nm FD-SOI” by Bashir et al., IEEE SOLID-STATE CIRCUITS LETTERS, VOL. 3, 2020, provides for example an additional upper electrode formed above the gate electrodes and at the first metal level of interconnections in order to control the tunnel coupling between two adjacent dots.
The effectiveness of such an additional electrode, in terms of modulation of potential that it allows to carry out, turns out to be insufficient. This is due in particular to the too-great distance between the additional electrode located in the first metal level and the semiconductor layer or “active zone” in which the qubits are formed.
This is also due to an electrostatic shielding effect because the gates are located in the stack between the additional electrode at the first metal level and the active zone.
The document “A new FDSOI spin qubit platform with 40 nm effective control pitch”, by T. Bédécarrats et al., IEDM 2021 also provides exchange electrodes called “J-gates” to control the tunnel coupling between two adjacent quantum dots. These exchange electrodes are this time in the form of conductive pads disposed above and facing the active zone. The control of the coupling between dots is improved insofar as the lower end of the pads is moved closer but the implementation of such electrodes poses problems of costs and difficulties of positioning the pads. It is indeed difficult to dispose these pads at a distance from the active zone sufficiently small to improve the coupling while avoiding coming in contact with the gate electrodes and the dots themselves. An effect of “shielding” by the gates persists with this configuration.
The problem of creating a new quantum device with one or more exchange electrodes and which is improved with respect to at least one of the disadvantages mentioned above thus arises.
According to one aspect, the present invention relates to a quantum electronic device comprising:
Such an arrangement of the exchange electrode allows to move closer to the active zone and consequently to the adjacent dots or to the quantum dot and to the dopant reservoir without undergoing an effect of screening of the front gates. With such exchange electrodes, improved control of the tunnel barrier between adjacent dots or between quantum dot and dopant reservoir can thus be obtained.
The creation of such exchange electrodes can also be carried out without risking creating contact on the semiconductor block.
Advantageously, at least one exchange electrode or each exchange electrode can be formed by a conductive pad or conductive via, in other words by a conductive element extending vertically or orthogonally to a main plane of the substrate and provided with an end corresponding to said lower end. The exchange electrode(s) is or are preferably located outside of a zone called “active zone” formed by the semiconductor block. In other words, the exchange electrode(s) are located outside of a vertical projection of the semiconductor block.
The exchange electrode(s) is or are preferably located outside of a zone called “active zone” formed by the semiconductor block but as close as possible to the latter.
Advantageously, the exchange electrode(s) are located on the same side of the substrate as the front gates. In other words, the exchange electrode(s) are not disposed at the rear of the substrate.
Advantageously, the exchange electrode(s) are made of a material that is not doped.
Advantageously, at least one front gate or each front gate comprises another part extending on one of the insulation zones.
Advantageously, at least one exchange electrode or each exchange electrode is disposed between two of said front gates.
The device can be provided with at least one first exchange electrode out of said exchange electrodes extending above the first insulation zone and at a distance from a first region of said semiconductor block forming a first quantum dot, the first exchange electrode being provided at a distance from a second region of said semiconductor block forming a second quantum dot and so as to allow to modulate a tunnel barrier between said first quantum dot and said second quantum dot.
The first exchange electrode can be formed by a conductive pad, said second conductive pad having a “lower” end disposed in contact with the second insulation zone or with an insulating material formed on said second insulation zone. The conductive pad typically passes through an insulating layer covering said semiconductor block and said insulation zones.
According to one possible embodiment, said second region of said semiconductor block forms a second quantum dot, the first exchange electrode being juxtaposed with a part of said semiconductor block arranged between said first region and said second region of said semiconductor block.
According to one possible embodiment, a second exchange electrode is arranged above a second insulation zone and is situated at a distance from said first region forming a first quantum dot and from said second region forming a second quantum dot, the second exchange electrode being configured to modulate the tunnel barrier between said first quantum dot and said second quantum dot, said second exchange electrode being formed by a second conductive pad, said second conductive pad having a “lower” end disposed in contact with the second insulation zone or with an insulating material formed on said second insulation zone.
According to one possible embodiment, the first exchange electrode is arranged between a first gate block and a second gate block, the first gate block and the second gate block extending mainly in a second direction orthogonal to the first direction.
According to one possible embodiment, the device can further comprise at least one other exchange electrode to modulate the tunnel barrier between the second quantum dot and a third quantum dot formed in a third region of the semiconductor block, the other exchange electrode being formed by a third conductive pad passing all the way through, the third conductive pad having a lower end in contact with the first insulation zone or the second insulation zone or an insulating material disposed on the first insulation zone or the second insulation zone.
According to one possible embodiment for which the third conductive pad can be disposed above and facing the first insulation zone and form a third exchange electrode, the device further comprises a fourth exchange electrode to modulate the tunnel barrier between the second quantum dot and a third quantum dot, the fourth exchange electrode being formed by a fourth conductive pad above and facing said second insulation zone.
According to one possible embodiment for which the first exchange electrode is provided to control the tunnel barrier between the first quantum dot and the second quantum dot, the device can be further provided with at least one additional exchange electrode provided to modulate a tunnel barrier between one of said quantum dots and a charge reservoir.
According to one possible embodiment, said lower end of each exchange electrode can be in contact with an etch stop layer or a dielectric layer in which insulating spacers of the front gates are formed.
Advantageously, the device can further comprise charge reservoirs formed on or in said semiconductor block, the charge reservoirs being arranged on either side of said front gates.
Advantageously, the device can further comprise a plurality of charge reservoir electrodes, each charge reservoir electrode contacting a charge reservoir formed on or in said semiconductor block.
According to one possible embodiment, the substrate is a substrate of the semiconductor on insulator type, said semiconductor block thus being formed in a surface semiconductor layer of the substrate.
According to another possible embodiment, the substrate is a bulk semiconductor substrate.
The semiconductor block can be formed by etching of a surface semiconductor layer of the substrate or by etching of a semiconductor layer deposited on this substrate, or by growth on this substrate.
According to another aspect, the present invention relates to a method for manufacturing a quantum electronic device as defined above.
According to another aspect, the present invention relates to a method for manufacturing a quantum device comprising, in this order, steps involving:
The method can further comprise, before the formation of the insulating layer, steps of:
According to one possible embodiment of the openings, said insulating material formed on the first insulation zone is that of said dielectric layer.
According to one possible embodiment, the method can further comprise, before the formation of the insulating layer and after the etching of the dielectric layer, the formation of doped regions on the end portions of the semiconductor block arranged on either side of all of the gate blocks.
According to one possible embodiment of the method, among the openings, at least one opening exposes a doped region of the semiconductor block,
The creation of the exchange electrode(s) can thus be concomitant to the creation of contacts on the charge reservoirs.
The present invention will be better understood upon reading the description of exemplary embodiments given, for purely informational and non-limiting purposes, while referring to the appended drawings in which:
Identical, similar or equivalent parts of the various drawings carry the same numerical references so as to facilitate the passage from one drawing to the other.
The various parts shown in the drawings are not necessarily shown according to a uniform scale, to make the drawings more readable.
Moreover, in the following description, terms that depend on the orientation of the structure such as “above”, “below”, “rear”, “front”, “peripheral” apply while considering that the structure is oriented in the manner illustrated in the drawings.
Reference is made first of all to
The substrate 10 thus includes a supporting layer 11 made of semiconductor material, a buried insulating layer 12 disposed on the support layer 11 and a semiconductor surface layer 13 disposed on the insulating layer. The substrate 10 is typically an SOI substrate, the surface layer 13 of which is made of silicon, in particular 28Si when this layer receives quantum dots forming electron-spin qubits.
The insulating layer 12 and the support layer 11 are typically, respectively, a layer made of silicon oxide usually called “BOX” (for Buried Oxide) and a semiconductor layer, for example containing silicon. The thickness of the surface layer 13 is for example between 5 nm and 50 nm, typically approximately 10 nm. The thickness of the buried insulating layer 12 is for example between 15 nm and 150 nm.
Other semiconductor materials are possible for the surface semiconductor layer 13. For hole-spin qubits, silicon can also be used or, according to one alternative, a heterostructure of the relaxed SiGe/stressed germanium/relaxed SiGe type can be chosen, the layer of hole qubits being that made of germanium.
Then, in the surface layer 13, at least one active zone pattern can be defined, here in the form of a semiconductor block 14, typically having an oblong or fin shape, for example parallelepipedic, and which extends mainly in a first direction. This can be done by photolithography and etching of the surface layer 13, in particular plasma etching with stoppage on the insulating layer 12.
Insulation zones 15A, 15B are then formed on either side of the active zone. The insulation zones 15A, 15B can be of the STI type (for Shallow Trench Isolation). The insulation zones 15A, 15B for example contain silicon oxide. The insulation zones 15A, 15B can be made by etching then depositing of insulating material. This can be followed by an optional planarisation to remove a thickness of insulating material and place the upper faces of the insulation zones 15A, 15B at the same level or substantially at the same level as the upper face of the semiconductor block 14.
In the specific exemplary embodiment illustrated in
A gate stack covering the semiconductor block 14 and the insulation zones 15A, 15B is then created. This stack is typically formed by at least one layer of gate dielectric and one or more layers of doped and/or metal semiconductor gate material(s).
For example the gate dielectric is formed by a silicon oxide. A “high-k” dielectric, in other words having a high dielectric constant k, such as for example HfO2 can also be used. There can be a metal layer such as for example TiN above which there is a layer of doped polysilicon above the dielectric itself to form the gate materials.
The gate stack can be coated with at least one masking layer, in particular with at least one hard mask layer typically formed by at least one insulating layer, for example made of SiN and/or made of SiO2.
A plurality of masking blocks 24a, 24c, 24d, 24e are then defined by etching in the masking layer in order to create a plurality of distinct blocks 22a, 22b, 22c, 22d, 22e in the gate stack. Anisotropic etching in particular using a plasma are carried out to create the masking blocks 24a, 24b, 24c, 24d, 24e, then the distinct gate blocks 22a, . . . , 22e under the latter and reproducing the patterns of the latter.
A structure obtained after this step is illustrated in
Each gate block can form a “front” gate electrode. Each front gate can be optionally independent and not connected to the other front gates and can thus be controlled independently of the other front gates.
A dielectric mask 27 can then be formed on and between the gate blocks. The dielectric mask 27 can be made here by deposition of a dielectric layer, carried out so as to cover the semiconductor block 14, the gate blocks 22a, . . . , 22e and the spaces between the gate blocks 22a, . . . , 22e. In the example illustrated in
The material of the dielectric mask 27 is for example chosen from one of the following materials: SiO2, SiN, SiCO, SiBCN, SiOCN. The method for depositing the dielectric mask 27 is preferably conformal, and in particular of the ALD type (for Atomic Layer Deposition) in order to fill the inter-gate spaces without creating a filling defect.
An etching of this dielectric layer is then carried out (
The dielectric mask 27 is removed from upper faces of end portions 223 of the blocks 22a, . . . , 22e and of “end” portions 148, 149 of the semiconductor block 14 located on either side of a central portion 140 of the semiconductor block 14 and of all of the gate blocks 22a, . . . , 22e and which are intended to receive charge reservoirs. The dielectric mask 27 is preserved on a central portion 140 of the semiconductor block 14 in which the dots are intended to be formed.
To complete the formation of the charge reservoirs on the portions 148, 149 of the semiconductor block 14, one or more layers of semiconductor material(s) 33 can then be grown by epitaxy on the exposed parts 14′, 14″ of the semiconductor block 14 (
An epitaxial growth of silicon or a CVD deposition (for chemical vapour deposition) for example of germanium can in particular be carried out. Doping is then carried out. This doping can be carried out by ion implantation and/or in situ doping carried out concomitantly to the growth of the layer(s) of semiconductor material(s) 33.
For example to form reservoirs 33a, 33b doped with n-type doping, a growth of Si:P (silicon doped with phosphorus) can be carried out. According to another example, to form reservoirs 33a, 33b doped with p-type doping, a growth of SiGe:B (silicon germanium doped with boron) can be carried out.
Because in particular of the presence of the dielectric layer 27 on a central portion 140 of the semiconductor block 14, a doping of this central portion 140 is thus avoided, this central portion 140 thus preferably remaining non-doped.
In the case in which one or more ion implantation(s) are carried out to form the reservoirs, a lithographic resin is preferably used to mask the central portion 140 and protect this portion from the implantation(s).
According to an optional step illustrated in
For this, portions of the masking blocks 24a, . . . , 24e arranged at the ends of the gate blocks 22a, . . . , 22e are removed (
Then, a step of depositing at least one layer of metal, for example Ni, Pt, W, Co, Ti, or V, can be carried out. The layer of metal can optionally be covered with an encapsulation layer that can be metal. An example of encapsulation is formed by depositing TiN, having a thickness for example of approximately 10 nm.
A heat treatment is then carried out to carry out the siliconising. Such a treatment can be implemented at a temperature of between 200° C. and 900° C. and a duration adapted according to the treatment temperature. A removal of the metal not having reacted can then be carried out for example by wet etching by using a hot solution of the SPM type (for Sulfuric Peroxide Mix). A second siliconising annealing can also be carried out.
In the exemplary embodiment illustrated in
The quantum device created has here the particularity of being provided with exchange electrodes allowing to implement a quantum coupling between neighbouring or adjacent regions of the semiconductor block 14 each intended for a quantum dot.
Thus, to create such exchange electrodes, at least one insulating layer 50 is first previously formed. The insulating layer 50 formed is provided to cover the semiconductor block 14, said insulation zones 15A, 15B, and the gate blocks 22a, . . . , 22e.
In the exemplary embodiment illustrated in
A first sublayer 51 made of insulating material, for example silicon nitride, is first of all created and forms here an etch stop layer. A deposition method of the PECVD type (plasma-enhanced chemical vapour deposition) can for example be used to form such a stop layer 51.
A second sublayer 52, for example silicon oxide (SiO2), is created on the first sublayer 51 and forms an encapsulation.
The first sublayer 51 or etch stop layer is preferably chosen made of a material different than that of the second sublayer 52 and of the insulation zones in order to better control the depth of the openings.
One or more openings 571, 572, 573, 574, 575, 576, 577, 578 are then made through the insulating layer 50 on either side of the semiconductor block 14. The openings can be made until the insulation zones 15A, 15B are reached. The creation of the openings 571, 572, 573, 574, 575, 576, 577, 578 is carried out typically by photolithography then via one or more etchings carried out through a mask (not shown).
In the exemplary embodiment illustrated in
According to an alternative embodiment (not shown), it is possible to extend these openings into the insulation zones 15A, 15B. The bottom of these openings 575, 577 can then be located in the thickness of the insulation zones 15A, 15B.
According to another possibility, the openings 571, 572, 573, 574, 575, 576, 577, 578 can have a bottom located at an insulating material disposed on the insulation zones 15A, 15B, for example at the masking dielectric layer 27.
In either case, creating the openings 571, 572, 573, 574, 575, 576, 577, 578 facing an insulation zone 15A or 15B rather than above the active zone allows in particular to get closer to the active zone without having to very precisely control the height at which their bottom is located.
In the specific exemplary embodiment illustrated in
Advantageously, concomitantly to the creation of the openings 571, 572, 573, 574, 575, 576, 577, 578 for receiving the exchange electrodes, it is possible to create one or more other openings through the insulating layer 50 and in particular openings 58, 59 to create contacts on the dopant reservoirs 33a, 33b. These openings 58, 59 thus have a bottom reaching the dopant reservoirs 33a, 33b or the silicided zones formed on these reservoirs.
Conductive pads 671, 672, 673, 674, 675, 676, 677, 678, 68, 69 are then formed by filling the openings 571, 572, 573, 574, 575, 576, 577, 578, 58, 59 using one or more conductive materials (
The conductive pads 671, 672, 673, 674, 675, 676, 677, 678 thus each form an exchange electrode. The conductive pads 671, 672, 673, 674, 675, 676, 677, 678 have a lower end 681 in contact with one of the insulation zones 15A, 15B.
The exchange electrodes 671, 672, 673, 674, 675, 676, 677, 678 are provided to modulate the potential barriers and consequently a tunnel barrier between two adjacent or neighbouring quantum dots near which these exchange electrodes are disposed.
The function of the exchange electrodes 671, 672, 673, 674, 675, 676, 677, 678 is distinct from that of the front gates, these exchange electrodes 671, 672, 673, 674, 675, 676, 677, 678 are not therefore connected to the front gates 22a, . . . , 22e. The exchange electrodes 671, 672, 673, 674, 675, 676, 677, 678 are not in contact with the semiconductor block 14 in which the dots are formed.
According to the levels of voltages that are applied to them, they thus modulate the quantum coupling between the quantum dots and therefore allow to carry out a control of the exchange energy between neighbouring quantum dots.
As for the conductive pads 68, 69, they act as contacts on the dopant reservoirs 33a, 33b. Contacts on the charge reservoirs and the exchange electrodes can thus be advantageously created concomitantly, without introducing a specific additional step to create these exchange electrodes, and in particular without an additional lithography step.
As illustrated in
“Near” means here at a non-zero distance preferably smaller than 20 nm and typically between 3 nm and 20 nm, preferably 3 nm and 10 nm, advantageously between 3 nm and 5 nm.
Each exchange electrode 671, 672, 673, 674, 675, 676, 677, 678 is positioned at a non-zero minimum distance Δmin from the semiconductor block preferably sufficient to avoid a tunnel current passing between this exchange electrode and the semiconductor block 14. A distance Δmin of at least 3 nm is preferably provided for this.
The first exchange electrode 671 is juxtaposed here with a part 141 of the central portion 140 of said semiconductor block 14, preferably not doped, which is arranged between the first region 14A forming the first dot and the second region 14B forming the second dot. In this specific configuration in which the gate blocks 22e, 22d respectively protrude from the regions 14A, 14B, the first exchange electrode 671 is arranged between a first gate block 22e and a second gate block 22d, these gate blocks 22e, 22d extending mainly in a direction orthogonal to that in which the semiconductor block 14 mainly extends. Such an arrangement also allows to have conductive pads close to the active zone while avoiding an effect of screening of the gates.
A pair of electrodes 671, 672 can advantageously be used to better modulate the tunnel barriers between a pair of neighbouring or adjacent dots.
Thus, in the specific exemplary embodiment illustrated, a second exchange electrode 672 provided on another side of the semiconductor block 14 is also disposed near said first region 14A forming the first quantum dot and the second region 14B forming a second quantum dot. The second exchange electrode 672 arranged above the second insulation zone 15B is also disposed at a given distance from the dots 15A, 15B chosen to allow to better modulate the potential barrier between said first quantum dot and said second quantum dot. The exchange electrode 672 is positioned at a distance Amin from the semiconductor block sufficient to allow preferably no tunnel current to pass between this electrode 672 and the semiconductor block 14.
The exchange electrodes 671, 672 can be in this case controlled independently of one another, so that the first electrode 671 can be set to a first potential while the second electrode 672 is set to a second potential different than the first potential. Thus, the electrodes 671, 672 can be independent of one another, in other words not connected or not linked to each other, and capable of receiving distinct potentials.
A third exchange electrode 673 and a fourth exchange electrode 674 are disposed here on either side of a part 142 of the semiconductor block 14 located between the second quantum dot and a third dot formed in a third region 14C of this semiconductor block 14. The third exchange electrode 673 and the fourth electrode 674 disposed respectively on the first insulation zone 15A and on the second insulation zone 15B are provided, according to the respective potential that are applied to them, to allow to be able to modulate the tunnel barrier between the second quantum dot formed in the region 14B and the third quantum dot formed in the region 14C.
In the exemplary embodiment illustrated, the electrodes 675, 676 disposed between the region 14C and the region 14D are provided to modulate the tunnel barrier between the neighbouring quantum dots respectively formed in these regions 14C, 14D. Likewise, the electrodes 677, 678 allow to modulate the tunnel barrier between a quantum dot formed in a region 14D and an adjacent quantum dot, here an end quantum dot of the succession or series of dots formed in the central portion of the semiconductor block 14.
Besides one or more exchange electrodes between dots, the quantum device can also be provided with one or more additional exchange electrodes this time between at least one quantum dot 14A or 14E located at an end of the succession of dots 14A, 14B, 14C, 14D, 14E and one of the dopant reservoirs R1, R2 located on either side of this succession of dots and formed in and/or from the semiconductor block 14.
In an exemplary embodiment illustrated in
The additional exchange electrodes 81, 82, 83, 84 are typically formed during the same method steps as the exchange electrodes 671, 672, 673, 674, 675, 676, 677, 678 as described above in relation to
To create these exchange electrodes 81, 82, 83, 84, openings in particular are formed in the insulating layer 50 each reaching the insulation zone 15A or the insulation zone 15B, then these openings are filled with at least one conductive material to form conductive pads in these openings.
The exchange electrodes 81, 82, 83, 84 are disposed on an insulation zone 15A or 15B and sufficiently close to the dopant reservoir R1 or R2 to, according to the level of potential that is applied to them, allow to modulate the coupling between this dopant reservoir R1, R2 and the end quantum dot 15A, 15E juxtaposed with this reservoir R1, R2.
An alternative embodiment is given in
The semiconductor bars 1410, 1420 have an oblong shape for example parallelepipedic and are separated from each other via a region 1450 typically made of insulating material.
This configuration of the central portion 140 of the semiconductor block can be obtained by creating a trench in the latter, and this trench can thus be filled with insulating material.
Above each dot of the first row, a front control gate 221 is arranged, and facing this gate 221, above each dot of the second row of detection dots, a control gate 222 is provided.
The dots of the first fin 1410 can be provided to form a first row of data qubits, while the dots of the second fin 1420 can form a second row of detection elements for the reading of an encoded value of the data qubits of the first row.
In either one of the exemplary embodiments described above, the semiconductor block in which the quantum dots are formed is made from the surface layer of a substrate, in particular a semiconductor on insulator substrate. However, it is also possible to start from a different substrate, for example a bulk substrate to form this block.
The semiconductor block(s) in which the quantum dots are formed can also be formed in one or more distinct semiconductor layers of a semiconductor surface layer of a substrate. Thus, according to a possible alternative, the semiconductor block for receiving quantum dots is formed by etching of a pattern created from one or more layers or zones formed by epitaxy.
According to a specific embodiment, the semiconductor block in which the quantum dots are provided can be in the form of a fin and implemented in a manner similar to that in which the semiconductor fin of a transistor of the finFET type is created.
A quantum device implemented according to the invention is not limited to a number of quantum dots and of front gates as given for example in
A device as described above can be provided with an electrode circuit for controlling the qubits and is adapted to the implementation on the same substrate of transistors for this control circuit. The transistors of the control circuit can use CMOS technology (Complementary metal-oxide-semiconductor), and in particular cryogenic CMOS, or cryo-CMOS, operating at low temperature and typically less than 1 Kelvin in order to best preserve the quantum states of the qubits.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2213369 | Dec 2022 | FR | national |
