Claims
- 1. A bus system for use with addressable memory comprising:
a master device; a global bus comprising bi-directional signal lines, the global bus having a first end at the master device and a second end; a global bus terminator coupled to the global bus at the second end; and one or more slave devices including a last slave device at a furthest distance from the master device, each slave device including an active terminator coupled to at least some of the bidirectional signal lines of the global bus, wherein the active terminator of the last slave device is enabled.
- 2. The bus system of claim 1 wherein a first portion of the global bus, extending from first end of the global bus to a point on the global bus to which the active terminator of the last slave device is coupled, has a first impedance ZOL, and a second portion of the global bus, extending from the point on the global bus to which the active terminator of the last slave device is coupled to the second end of the global, has a second impedance ZOH, the global bus terminator has an impedance of ZOH, and the active terminator of the last slave device has an impedance equal to ZOL·ZOH/(ZOH−ZOL).
- 3. The expandable system of claim 1 wherein the global bus has a first impedance when outputting a low voltage ZOL, and a second impedance when outputting a high voltage ZOH, the global bus terminator has an impedance of ZOH and the active terminator has an impedance approximately equal to ZOL·ZOH/(ZOH−ZOL).
- 4. The expandable system of claim 1 wherein bi-directional signal lines include a plurality of data lines for conveying data signals, and the active terminator of the last slave device is coupled to all the data lines of the bidirectional signal lines.
- 5. The expandable system of claim 1 wherein the master device is a memory controller and the one or more slave devices include one or more random access memory devices.
- 6. The expandable system of claim 1 wherein the master device is a memory controller and the one or more slave devices include one or more semiconductor random access memory devices.
- 7. The expandable system of claim 1 wherein a state of the active terminator of the last slave device is electronically controlled by signals from a control bus.
- 8. An expandable system, comprising:
a master device; a global bus comprising bi-directional signal lines, the global bus having a first end at the master device and a second end; a global bus terminator coupled to the global bus at the second end; and a first slave device having a first terminator coupled to the global bus, wherein the first terminator is inactive when any other slave device is located further from the master device than the first slave device and active when the first slave device is furthest from the master device.
- 9. The expandable system of claim 8, wherein the first slave device is a first memory device.
- 10. The expandable system of claim 9, wherein the any other slave device is any other memory device.
- 11. The expandable system of claim 8, wherein bidirectional signal lines include a plurality of data lines for conveying data signals, and the first terminator of the last slave device is coupled to all the data lines of the bi-directional signal lines.
- 12. The expandable system of claim 8, wherein the master device is a memory controller and the first slave device is a random access memory device.
- 13. The expandable system of claim 8, wherein a state of the first terminator is electronically controlled by signals from a control bus.
- 14. A clock selection circuit comprising:
a first delay locked loop to receive a first clock signal; a second delay locked loop; and a multiplexor coupled to the second delay locked loop to receive the first clock signal and a second clock signal, and to supply either the first clock signal or the second clock signal as a selected clock signal to the second delay locked loop in response to a control signal.
- 15. The clock selection circuit of claim 14 wherein one of the first and second clock signals is a receive clock signal and the other one of the first and second clock signals is a transmit clock signal.
- 16. A memory comprising:
a receiver to receive incoming data; an output driver to transmit outgoing data; and a clock selection circuit comprising:
a first delay locked loop to receive an external receive clock signal, the receive clock signal to synchronize the timing of the incoming data; a second delay locked loop; and a multiplexor to receive the external receive clock signal and an external transmit clock signal, and to supply either the external receive clock signal or the external transmit clock signal as a selected internal transmit clock signal to the second delay locked loop in response to a control signal, wherein the output driver transmits the outgoing data in accordance with the selected internal transmit clock signal.
Parent Case Info
[0001] This is a divisional application of U.S. patent application Ser. No. 09/706,238 filed Nov. 2, 2000 entitled, “Expandable Slave Device System”, which is hereby incorporated by reference.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09706238 |
Nov 2000 |
US |
Child |
10738293 |
Dec 2003 |
US |