with synchronous protocol

Industry

CPC
G06F13/4243

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Current Industry

G06F13/4243with synchronous protocol

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Memory module with data buffering
- Patent number 12,222,878
- Issue date Feb 11, 2025
- Netlist, Inc.
- Jefferey C. Solomon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system and method of controlling a memory chip
- Patent number 12,154,659
- Issue date Nov 26, 2024
- Kioxia Corporation
- Shinya Koizumi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer architecture having selectable parallel and serial communi...
- Patent number 12,140,992
- Issue date Nov 12, 2024
- Wisconsin Alumni Research Foundation
- Hao Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-power source-synchronous signaling
- Patent number 12,119,042
- Issue date Oct 15, 2024
- RAMBUS INC.
- Jared L. Zerbe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for command bus training to a memory device
- Patent number 12,093,195
- Issue date Sep 17, 2024
- Intel Corporation
- Christopher P. Mozak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for detecting and configuring lanes in a circui...
- Patent number 12,087,381
- Issue date Sep 10, 2024
- Altera Corporation
- Marian Cretu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface clock management
- Patent number 12,032,508
- Issue date Jul 9, 2024
- RAMBUS INC.
- Yuanlong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double data rate (DDR) memory controller apparatus and method
- Patent number 12,014,767
- Issue date Jun 18, 2024
- Uniquify, Inc.
- Mahesh Gopalan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data transmission using delayed timing signals
- Patent number 11,990,912
- Issue date May 21, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage controller, storage device including the same, and operatio...
- Patent number 11,940,862
- Issue date Mar 26, 2024
- Samsung Electronics Co., Ltd.
- Hyun Ju Yi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable server and server rack with same
- Patent number 11,907,152
- Issue date Feb 20, 2024
- Molex, LLC
- Augusto Panella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High capacity memory system with improved command-address and chip-...
- Patent number 11,899,597
- Issue date Feb 13, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quasi-synchronous protocol for large bandwidth memory systems
- Patent number 11,893,239
- Issue date Feb 6, 2024
- Samsung Electronics Co., Ltd.
- Krishna T. Malladi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Status signal output
- Patent number 11,868,302
- Issue date Jan 9, 2024
- WAGO Verwaltungsgesellschaft mbH
- Daniel Jerolm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory interface for a multi-threaded, self-scheduling reconfigurab...
- Patent number 11,836,524
- Issue date Dec 5, 2023
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system and method of controlling a memory chip
- Patent number 11,830,576
- Issue date Nov 28, 2023
- Kioxia Corporation
- Shinya Koizumi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer architecture having selectable, parallel and serial commun...
- Patent number 11,755,060
- Issue date Sep 12, 2023
- Wisconsin Alumni Research Foundation
- Hao Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-power source-synchronous signaling
- Patent number 11,749,336
- Issue date Sep 5, 2023
- RAMBUS INC.
- Jared L. Zerbe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double data rate (DDR) memory controller apparatus and method
- Patent number 11,710,516
- Issue date Jul 25, 2023
- Uniquify, Inc.
- Mahesh Gopalan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface clock management
- Patent number 11,681,648
- Issue date Jun 20, 2023
- RAMBUS INC.
- Yuanlong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for command bus training to a memory device
- Patent number 11,675,716
- Issue date Jun 13, 2023
- Intel Corporation
- Christopher P. Mozak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system component that enables clock-to-strobe skew compensation
- Patent number 11,664,067
- Issue date May 30, 2023
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frame protocol of memory device
- Patent number 11,580,049
- Issue date Feb 14, 2023
- Micron Technology, Inc.
- James Brian Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronous memory bus access to storage media
- Patent number 11,544,207
- Issue date Jan 3, 2023
- Micron Technology, Inc.
- Paul Stonelake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communicating non-isochronous data over an isochronous channel
- Patent number 11,537,544
- Issue date Dec 27, 2022
- Cirrus Logic, Inc.
- Bradley A. Lambert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Status signal output
- Patent number 11,537,549
- Issue date Dec 27, 2022
- WAGO Verwaltungsgesellschaft mbH
- Daniel Jerolm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable server and server rack with same
- Patent number 11,513,990
- Issue date Nov 29, 2022
- Molex, LLC
- Augusto Panella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for managing requests for access to random access memory and...
- Patent number 11,495,275
- Issue date Nov 8, 2022
- STMicroelectronics (Rousset) SAS
- Christophe Eva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system with region-specific memory access scheduling
- Patent number 11,474,703
- Issue date Oct 18, 2022
- Advanced Micro Devices, Inc.
- Yi Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller for selective rank or subrank access
- Patent number 11,467,986
- Issue date Oct 11, 2022
- RAMBUS INC.
- Craig E. Hampel
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY SYSTEM AND METHOD OF CONTROLLING A MEMORY CHIP
- Publication number 20250095703
- Publication date Mar 20, 2025
- KIOXIA Corporation
- Shinya KOIZUMI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-POWER SOURCE-SYNCHRONOUS SIGNALING
- Publication number 20250069644
- Publication date Feb 27, 2025
- Rambus Inc.
- Jared L. ZERBE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE CLOCK MANAGEMENT
- Publication number 20240403255
- Publication date Dec 5, 2024
- Rambus Inc.
- Yuanlong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Computer Architecture Having Selectable Parallel and Serial Communi...
- Publication number 20240402752
- Publication date Dec 5, 2024
- Wisconsin Alumni Research Foundation
- Hao Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR COMMAND BUS TRAINING TO A MEMORY DEVICE
- Publication number 20240370390
- Publication date Nov 7, 2024
- Intel Corporation
- Christopher P. MOZAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA TRANSMISSION USING DELAYED TIMING SIGNALS
- Publication number 20240372542
- Publication date Nov 7, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE AND MODULAR BUS CONTROLLER INCLUDING PAGE MEMORY PLD ARCHI...
- Publication number 20240345984
- Publication date Oct 17, 2024
- HAMILTON SUNDSTRAND CORPORATION
- Rajesh Madathikandam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data Processing System and Method
- Publication number 20240338328
- Publication date Oct 10, 2024
- Huawei Technologies Co., Ltd
- Wen Yin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
- Publication number 20240290372
- Publication date Aug 29, 2024
- Uniquify, Inc.
- Mahesh GOPALAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATED DRAM (DYNAMIC RANDOM ACCESS MEMORY) TRAINING
- Publication number 20240241842
- Publication date Jul 18, 2024
- Intel Corporation
- Saravanan SETHURAMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORAGE CONTROLLER, STORAGE DEVICE INCLUDING THE SAME, AND OPERATIO...
- Publication number 20240201774
- Publication date Jun 20, 2024
- Samsung Electronics Co., Ltd.
- HYUN JU YI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-...
- Publication number 20240193108
- Publication date Jun 13, 2024
- Rambus Inc.
- Frederick A. WARE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATUS SIGNAL OUTPUT
- Publication number 20240111708
- Publication date Apr 4, 2024
- WAGO VERWALTUNGSGESELLSCHAFT MBH
- Daniel JEROLM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
- Publication number 20240112721
- Publication date Apr 4, 2024
- Uniquify, Inc.
- Mahesh GOPALAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-POWER SOURCE-SYNCHRONOUS SIGNALING
- Publication number 20240021236
- Publication date Jan 18, 2024
- Rambus Inc.
- Jared L. Zerbe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Computer Architecture Having Selectable Parallel and Serial Communi...
- Publication number 20240004419
- Publication date Jan 4, 2024
- Wisconsin Alumni Research Foundation
- Hao Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE CLOCK MANAGEMENT
- Publication number 20230350835
- Publication date Nov 2, 2023
- Rambus Inc.
- Yuanlong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER WITH SKEW COMPENSATED DATA TRANSMIT TIMING
- Publication number 20230335177
- Publication date Oct 19, 2023
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR COMMAND BUS TRAINING TO A MEMORY DEVICE
- Publication number 20230297523
- Publication date Sep 21, 2023
- Intel Corporation
- Christopher P. MOZAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM WITH REGION-SPECIFIC MEMORY ACCESS SCHEDULING
- Publication number 20230142598
- Publication date May 11, 2023
- ADVANCED MICRO DEVICES, INC.
- Yi XU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE SERVER AND SERVER RACK WITH SAME
- Publication number 20230079644
- Publication date Mar 16, 2023
- Molex, LLC
- Augusto PANELLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data Transmission Using Delayed Timing Signals
- Publication number 20230073567
- Publication date Mar 9, 2023
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATUS SIGNAL OUTPUT
- Publication number 20230026273
- Publication date Jan 26, 2023
- WAGO VERWALTUNGSGESELLSCHAFT MBH
- Daniel JEROLM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM AND DATA TRANSMISSION METHOD
- Publication number 20230018344
- Publication date Jan 19, 2023
- Longitude Licensing Limited
- Yoshinori Matsui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE SERVER AND SERVER RACK WITH SAME
- Publication number 20220358076
- Publication date Nov 10, 2022
- Molex, LLC
- Augusto PANELLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
- Publication number 20220254403
- Publication date Aug 11, 2022
- Uniquify, Inc.
- Mahesh GOPALAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE CLOCK MANAGEMENT
- Publication number 20220222197
- Publication date Jul 14, 2022
- Rambus Inc.
- Yuanlong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-...
- Publication number 20220222189
- Publication date Jul 14, 2022
- Rambus Inc.
- Frederick A. WARE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLASH-DRAM HYBRID MEMORY MODULE
- Publication number 20220222191
- Publication date Jul 14, 2022
- Netlist, Inc.
- Chi-She Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-POWER SOURCE-SYNCHRONOUS SIGNALING
- Publication number 20220130445
- Publication date Apr 28, 2022
- Rambus Inc.
- Jared L. Zerbe
- G06 - COMPUTING CALCULATING COUNTING

with synchronous protocol

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Memory module with data buffering

Memory system and method of controlling a memory chip

Computer architecture having selectable parallel and serial communi...

Low-power source-synchronous signaling

Techniques for command bus training to a memory device

Systems and methods for detecting and configuring lanes in a circui...

Interface clock management

Double data rate (DDR) memory controller apparatus and method

Data transmission using delayed timing signals

Storage controller, storage device including the same, and operatio...

Reconfigurable server and server rack with same

High capacity memory system with improved command-address and chip-...

Quasi-synchronous protocol for large bandwidth memory systems

Status signal output

Memory interface for a multi-threaded, self-scheduling reconfigurab...

Memory system and method of controlling a memory chip

Computer architecture having selectable, parallel and serial commun...

Low-power source-synchronous signaling

Double data rate (DDR) memory controller apparatus and method

Interface clock management

Techniques for command bus training to a memory device

Memory system component that enables clock-to-strobe skew compensation

Frame protocol of memory device

Synchronous memory bus access to storage media

Communicating non-isochronous data over an isochronous channel

Status signal output

Reconfigurable server and server rack with same

Method for managing requests for access to random access memory and...

Memory system with region-specific memory access scheduling

Memory controller for selective rank or subrank access

Patents Applicationslast 30 patents

MEMORY SYSTEM AND METHOD OF CONTROLLING A MEMORY CHIP

LOW-POWER SOURCE-SYNCHRONOUS SIGNALING

INTERFACE CLOCK MANAGEMENT

Computer Architecture Having Selectable Parallel and Serial Communi...

TECHNIQUES FOR COMMAND BUS TRAINING TO A MEMORY DEVICE

DATA TRANSMISSION USING DELAYED TIMING SIGNALS

SCALABLE AND MODULAR BUS CONTROLLER INCLUDING PAGE MEMORY PLD ARCHI...

Data Processing System and Method

DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD

ACCELERATED DRAM (DYNAMIC RANDOM ACCESS MEMORY) TRAINING

STORAGE CONTROLLER, STORAGE DEVICE INCLUDING THE SAME, AND OPERATIO...

HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-...

STATUS SIGNAL OUTPUT

DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD

LOW-POWER SOURCE-SYNCHRONOUS SIGNALING

Computer Architecture Having Selectable Parallel and Serial Communi...

INTERFACE CLOCK MANAGEMENT

MEMORY CONTROLLER WITH SKEW COMPENSATED DATA TRANSMIT TIMING

TECHNIQUES FOR COMMAND BUS TRAINING TO A MEMORY DEVICE

MEMORY SYSTEM WITH REGION-SPECIFIC MEMORY ACCESS SCHEDULING

RECONFIGURABLE SERVER AND SERVER RACK WITH SAME

Data Transmission Using Delayed Timing Signals

STATUS SIGNAL OUTPUT

MEMORY SYSTEM AND DATA TRANSMISSION METHOD

RECONFIGURABLE SERVER AND SERVER RACK WITH SAME

DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD

INTERFACE CLOCK MANAGEMENT

HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-...

FLASH-DRAM HYBRID MEMORY MODULE

LOW-POWER SOURCE-SYNCHRONOUS SIGNALING