Extended landing pad substrate package structure and method

Abstract

An extended landing pad substrate package includes a dielectric layer having an upper surface and an opposite lower surface. A lower circuit pattern is embedded in the lower surface of the dielectric layer. The lower circuit pattern includes traces having a first thickness and extended landing pads having a second thickness greater than the first thickness. Blind via apertures are formed through an upper circuit pattern embedded into the upper surface of the dielectric layer, through the dielectric layer and to the extended landing pads. The length of the blind via apertures is minimized due to the increase second thickness of the extended landing pads as compared to the first thickness of traces. Accordingly, the width of the blind via apertures at the upper surface of the dielectric layer is minimized.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present application relates to the field of electronics, and more particularly, to methods of forming electronic component packages and related structures.

2. Description of the Related Art

During fabrication of an electronic component package substrate, an upper circuit pattern is formed on or embedded within an upper surface of a dielectric layer. Similarly, a lower circuit pattern is formed on or embedded within a lower surface of the dielectric layer.

To electrically interconnect the upper circuit pattern with the lower circuit pattern through the dielectric layer, blind via apertures are formed through the upper circuit pattern and the dielectric layer to expose portions of the lower circuit pattern. The blind via apertures are filled with electrically conductive material to form blind vias electrically interconnecting the upper circuit pattern with the lower circuit pattern.

The blind via apertures are formed using laser-ablation, i.e., by using a laser to ablate through the upper circuit pattern and the dielectric layer to form the blind via apertures. Accordingly, the blind via apertures taper, i.e., are not perfectly cylindrical.

More particularly, the blind via apertures have a greater width at the upper circuit pattern than at the lower circuit pattern. The relatively large width of the blind via apertures at the upper circuit pattern places fundamental restrictions on the ability to minimize the feature size of the substrate.

SUMMARY OF THE INVENTION

In accordance with one embodiment, an extended landing pad substrate package includes a dielectric layer having an upper surface and an opposite lower surface. A lower circuit pattern is embedded in the lower surface of the dielectric layer. The lower circuit pattern includes traces having a first thickness and extended landing pads having a second thickness greater than the first thickness.

Blind via apertures are formed through an upper circuit pattern embedded into the upper surface of the dielectric layer, through the dielectric layer and to the extended landing pads. The length of the blind via apertures is minimized due to the increased second thickness of the extended landing pads as compared to the first thickness of traces. Accordingly, the width of the blind via apertures at the upper surface of the dielectric layer is minimized. Accordingly, extremely small blind via apertures are formed even when the dielectric layer is relatively thick. This enables the upper circuit pattern to be formed with minimum feature size.

These and other features of the present invention will be more readily apparent from the detailed description set forth below taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an extended landing pad substrate package formation method in accordance with one embodiment;

FIG. 2 is a cross-sectional view of an extended landing pad substrate package during fabrication in accordance with one embodiment;

FIGS. 3, 4, 5, 6, 7, 8 are cross-sectional views of the extended landing pad substrate package of FIG. 2 at later stages during fabrication in accordance with various embodiments;

FIG. 9 is a cross-sectional view of an upper circuit pattern carrier structure of the extended landing pad substrate package in accordance with one embodiment;

FIGS. 10, 11, 12 are cross-sectional view of the upper circuit pattern carrier structure of the extended landing pad substrate package of FIG. 9 at later stages during fabrication in accordance with various embodiments;

FIG. 13 is a cross-sectional view of the extended landing pad substrate package of FIGS. 8, 12 at a later stage during fabrication in accordance with one embodiment;

FIG. 14, 15, 16, 17 are cross-sectional views of the extended landing pad substrate package of FIG. 13 at later stages during fabrication in accordance with various embodiments; and

FIG. 18 is a cross-sectional view of the extended landing pad substrate package of FIG. 16 at a later stage during fabrication in accordance with another embodiment.

In the following description, the same or similar elements are labeled with the same or similar reference numbers.

DETAILED DESCRIPTION

As an overview, referring to FIG. 15, an extended landing pad substrate package 200 includes a dielectric layer 1340 having an upper surface 1340U and an opposite lower surface 1340L. A lower circuit pattern 834 is embedded in lower surface 1340L of dielectric layer 1340. Lower circuit pattern 834 includes traces 418 having a first thickness T1 and extended landing pads 732 having a second thickness T2 greater than first thickness T1.

Blind via apertures 1544 are formed through an upper circuit pattern 1234 embedded into upper surface 1340U of dielectric layer 1340, through dielectric layer 1340 and to extended landing pads 732. The length L1 of blind via apertures 1544 is minimized due to the increased thickness T2 of extended landing pads 732 as compared to thickness T1 of traces 418. Accordingly, the width W3 of blind via apertures 1544 at upper surface 1340U of dielectric layer 1340 is minimized. Accordingly, extremely small blind via apertures 1544 are formed even when dielectric layer 1340 is relatively thick. This enables upper circuit pattern 1234 to be formed with minimum feature size.

In one embodiment, by minimizing length L1 of blind via apertures 1544, tolerance in the alignment between blind via apertures 1544 and extended landing pads 732 is minimized. This enables the width of extended landing pads 732 in a direction parallel to lower surface 1340L of dielectric layer 1340 to be minimized. This, in turn, enables lower circuit pattern 834 to be formed with minimum feature size.

In one embodiment, by minimizing length L1 of blind via apertures 1544, the time required to form blind via apertures 1544 is minimized thus minimizing the cost of the blind via laser-ablation process and thus of extended landing pad substrate package 200.

More particularly, FIG. 1 is an extended landing pad substrate package formation method 100 in accordance with one embodiment. FIG. 2 is a cross-sectional view of an extended landing pad substrate package 200 during fabrication in accordance with one embodiment. Referring now to FIGS. 1 and 2 together, in a form seed layer on carrier operation 102, a seed layer 202 is formed on a carrier 204.

Carrier 204 is an electrically conductive material, e.g., copper, although is formed of other conductive materials in other embodiments. In yet another embodiment, carrier 204 is a dielectric material.

Carrier 204 includes a first surface 204U and an opposite second surface 204L. Seed layer 202 is formed, e.g., by plating a conductive material or applying a conductive foil, on first surface 204U of carrier 202. As illustrated in FIG. 2, seed layer 202 entirely covers upper surface 204U of carrier 204. Seed layer 202 is an electrically conductive material, e.g., copper.

From form seed layer on carrier operation 102, flow moves to an apply primary resist to seed layer operation 104. In apply primary resist to seed layer operation 104, a primary resist 206 is applied to seed layer 202. As illustrated in FIG. 2, primary resist 206 entirely covers seed layer 202. Primary resist 206, e.g., photoresist, is a dielectric material.

FIG. 3 is a cross-sectional view of extended landing pad substrate package 200 of FIG. 2 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 1 and 3 together, from apply primary resist to seed layer operation 104, flow moves to a pattern primary resist operation 106. In pattern primary resist operation 106, primary resist 206 is patterned to form a circuit pattern artifact 308 within primary resist 206.

Circuit pattern artifact 308, i.e., a patterned opening within primary resist 206, is a positive image of the circuit pattern to be formed. More particularly, primary resist 206 is patterned to expose exposed portions 314 of seed layer 202 through circuit pattern artifact 308. Primary resist 206 is patterned using any one of a number of resist patterning techniques such as laser-ablation or photo-imaging, and the particular technique used is not essential to this embodiment.

Circuit pattern artifact 308 includes a trace pattern artifact 310 and an extended landing pad pattern artifact 312. Trace pattern artifact 310, i.e., a first portion of the patterned opening within primary resist 206, is a positive image of the traces of the circuit pattern to be formed. Extended landing pad pattern artifact 312, i.e., a second portion of the patterned opening within primary resist 206, is a positive image of the extended landing pads of the circuit pattern to be formed.

FIG. 4 is a cross-sectional view of extended landing pad substrate package 200 of FIG. 3 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 1, 3 and 4 together, from pattern primary resist operation 106, flow moves to a plate primary conductor layer operation 108. In plate primary conductor layer operation 108, a primary conductor layer 416 is plated within circuit pattern artifact 308 of primary resist 206. Primary conductor layer 416 is formed of an electrically conductive material such as copper, sometimes called a circuit pattern metal.

Primary conductor layer 416 is plated on seed layer 202 using primary resist 206 as a mask. More particularly, primary conductor layer 416 is plated on exposed portions 314 of seed layer 202, e.g., using seed layer 202 as the electroplating electrode.

Illustratively, primary conductor layer 416 includes electrically conductive traces 418 and extended landing pad foundation portions 420. More particularly, traces 418 are formed within trace pattern artifact 310 of circuit pattern artifact 308. Extended landing pad foundation portions 420 are formed within extending landing pad pattern artifact 312 of circuit pattern artifact 308.

For simplicity of presentation, only two traces 418 and a single extended landing pad foundation portion 420 are illustrated in the figures. However, in light of this disclosure, those of skill in the art will understand that a plurality of traces 418 and extended landing pad foundation portions 420 and the associated structures as discussed below are formed.

In accordance with this embodiment, primary conductor layer 416 only partially fills circuit pattern artifact 308. More particularly, the thickness T1 of primary conductor layer 416 is less than the thickness T2 of primary resist 206. Accordingly, an unfilled portion 421 of circuit pattern artifact 308 remains empty.

FIG. 5 is a cross-sectional view of extended landing pad substrate package 200 of FIG. 4 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 1, 4 and 5 together, from plate primary conductor layer operation 108, flow moves to an apply secondary resist operation 110. In apply secondary resist operation 110, a secondary resist 522, e.g., photoresist, is applied to entirely cover primary resist 206 and primary conductor layer 416 as illustrated in FIG. 5. Secondary resist 522 fills unfilled portion 421 of circuit pattern artifact 308. In one embodiment, secondary resist 522 is a dielectric material.

FIG. 6 is a cross-sectional view of extended landing pad substrate package 200 of FIG. 5 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 1 and 6 together, from apply secondary resist operation 110, flow moves to a pattern secondary resist operation 112. In pattern secondary resist operation 112, secondary resist 522 is patterned to form an extended landing pad overlay pattern artifact 624 within secondary resist 522.

Extended landing pad overlay pattern artifact 624, i.e., a patterned opening within secondary resist 522, is a positive image of the extended landing pads to be formed. More particularly, secondary resist 522 is patterned to expose extended landing pad foundation portions 420 of primary conductor layer 416 through extended landing pad overlay pattern artifact 624. Secondary resist 522 is patterned using any one of a number of resist patterning techniques such as laser-ablation or photo-imaging, and the particular technique used is not essential to this embodiment.

In one embodiment, to accommodate for tolerance between the patterning of primary resist 206 and secondary resist 522, extended landing pad overlay pattern artifact 624 is formed with a greater width W1 then the width W2 of extended landing pad pattern artifact 312 (and thus extending landing pad foundation portions 420). Accordingly, portions 626 of primary resist 206 adjacent extended landing pad pattern artifact 312 (and extending landing pad foundation portions 420) are exposed.

Secondary resist 522 remains over traces 418 of primary conductor layer 416 thus protecting traces 418 from additive plating as discussed below.

FIG. 7 is a cross-sectional view of extended landing pad substrate package 200 of FIG. 6 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 1, 6 and 7 together, from pattern secondary resist operation 112, flow moves to a plate secondary conductor layer operation 114. In plate secondary conductor layer operation 114, a secondary conductor layer 728 is plated on primary conductor layer 416 using primary resist 206 and secondary resist 522 as a mask.

More particularly, secondary conductor layer 728 is plated on extended landing pad foundation portions 420 of primary conductor layer 416, e.g., using primary conductor layer 416 as the electroplating electrode.

Secondary conductor layer 728 is plated within extending landing pad pattern artifact 312 of primary resist 206 through extended landing pad overlay pattern artifact 624 of secondary resist 522. Secondary conductor layer 728 is formed of an electrically conductive material such as copper, sometimes called an extended landing pad extension metal.

In accordance with this embodiment, secondary conductor layer 728 completely fills unfilled portion 421 of extending landing pad pattern artifact 312. In one embodiment, secondary conductor layer 728 is over plated to cover portions 626 of primary resist 206 and then etched to expose portions 626 of primary resist 206 to ensure that unfilled portion 421 of extending landing pad pattern artifact 312 is completely filled. Secondary resist 522 covers and protects traces 418 and thus secondary conductor layer 728 is not formed on traces 418.

Secondary conductor layer 728 forms extended landing pad extension portions 730. As set forth above, extended landing pad extension portions 730 are selectively plated on extended landing pad foundation portions 420. Collectively, extended landing pad foundation portions 420 and extended landing pad extension portions 730 form extended landing pads 732.

Extended landing pads 732 have thickness T2 of primary resist 206. Accordingly, by selecting the desired thickness T2 of primary resist 206, the thickness T2 of extended landing pads 732 is precisely controlled. Recall that traces 418 have thickness T1 less than thickness T2 of extended landing pads 732.

FIG. 8 is a cross-sectional view of extended landing pad substrate package 200 of FIG. 7 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 1, 7 and 8 together, from plate secondary conductor layer operation 114, flow moves to a strip primary resist and secondary resist operation 116. In strip primary resist and secondary resist operation 116, primary resist 206 and secondary resist 522 are stripped, i.e., removed. Primary resist 206 and secondary resist 522 are stripped using any one of a number of techniques and the particular technique used is not essential to this embodiment.

Paying particular attention now to FIGS. 1 and 8 together, after performance of strip primary resist and secondary resist operation 116, a lower, e.g., first, circuit pattern 834 remains upon seed layer 202 and generally on carrier 204. Lower circuit pattern 834 includes traces 418 and extended landing pads 732. Traces 418 are electrical conductors extending in the horizontal, e.g., first, direction substantially parallel to first surface 204U of carrier 204. Extended landing pads 732 are electrically interconnected to traces 418.

As discussed above, traces 418 have thickness T1 less than thickness T2 of extended landing pads 732. More particularly, thickness T1 and thickness T2 are measured in the vertical, e.g., second, direction substantially perpendicular to first surface 204U of carrier 204.

Extended landing pad substrate package 200 at the stage illustrated in FIG. 8 is sometimes referred to as a lower, e.g., first, circuit pattern carrier structure 836. More particularly, lower circuit pattern carrier structure 836, sometimes called a second layer transfer template, includes carrier 204, seed layer 202, and lower circuit pattern 834.

As discussed below with reference to operations 118, 120, 122, 124, 126 and FIGS. 1, 9, 10, 11, 12, an upper circuit pattern carrier structure is also formed separately from lower circuit pattern carrier structure 836.

FIG. 9 is a cross-sectional view of an upper, e.g., second, circuit pattern carrier structure 900 of extended landing pad substrate package 200 in accordance with one embodiment. Referring now to FIGS. 1 and 9 together, in a form seed layer on carrier operation 118, a seed layer 202 is formed on a carrier 204. Seed layer 202 and carrier 204 are similar to seed layer 202 and carrier 204 as discussed above in reference to FIG. 2 and so the description thereof is not repeated here.

From form seed layer on carrier operation 118, flow moves to an apply resist to seed layer operation 120. In apply resist to seed layer operation 120, a resist 906 is applied to seed layer 202. As illustrated in FIG. 9, resist 906 entirely covers seed layer 202. Resist 906, e.g., photoresist, is a dielectric material. In one embodiment, thickness T2 of primary resist 206 (see FIG. 4) is greater than a thickness T3 of resist 906, e.g., primary resist 206 is two to three times thicker than resist 906.

FIG. 10 is a cross-sectional view of upper circuit pattern carrier structure 900 of extended landing pad substrate package 200 of FIG. 9 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 1 and 10 together, from apply resist to seed layer operation 120, flow moves to a pattern resist operation 122. In pattern resist operation 122, resist 906 is patterned to form a circuit pattern artifact 1008 within resist 906.

Circuit pattern artifact 1008, i.e., a patterned opening within resist 906, is a positive image of the circuit pattern to be formed. More particularly, resist 906 is patterned to expose exposed portions 1014 of seed layer 202 through circuit pattern artifact 1008. Resist 906 is patterned using any one of a number of resist patterning techniques such as laser-ablation or photo-imaging, and the particular technique used is not essential to this embodiment.

FIG. 11 is a cross-sectional view of upper circuit pattern carrier structure 900 of extended landing pad substrate package 200 of FIG. 10 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 1, 10 and 11 together, from pattern resist operation 122, flow moves to a plate conductor layer operation 124. In plate conductor layer operation 124, a conductor layer 1116 is plated within circuit pattern artifact 1008 of resist 906. Conductor layer 1116 is formed of an electrically conductive material such as copper, sometimes called a circuit pattern metal.

Conductor layer 1116 is plated on seed layer 202 using resist 906 as a mask. More particularly, conductor layer 1116 is plated on exposed portions 1014 of seed layer 202, e.g., using seed layer 202 as the electroplating electrode. In accordance with this embodiment, conductor layer 1116 completely fills circuit pattern artifact 1008. More particularly, conductor layer 1116 and resist 906 have an approximately equal thickness T3.

FIG. 12 is a cross-sectional view of upper circuit pattern carrier structure 900 of extended landing pad substrate package 200 of FIG. 11 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 1, 11 and 12 together, from plate conductor layer operation 124, flow moves to a strip resist operation 126. In strip resist operation 126, resist 906 is stripped, i.e., removed. Resist 906 is stripped using any one of a number of techniques and the particular technique used is not essential to this embodiment. At the stage illustrated in FIG. 12, fabrication of upper circuit pattern carrier structure 900, sometimes called a first layer transfer template, is complete.

Upper circuit pattern carrier structure 900 includes carrier 204, seed layer 202, and an upper, e.g., second, circuit pattern 1234 formed by conductor layer 1116. Upper circuit pattern 1234 remains upon seed layer 202 and generally on carrier 204. Upper circuit pattern 1234 includes traces, landing pads and/or other electrically conductive features.

Upper circuit pattern 1234 has thickness T3. More particularly, thickness T3 is measured in the vertical direction substantially perpendicular to first surface 204U of carrier 204.

FIG. 13 is a cross-sectional view of extended landing pad substrate package 200 of FIGS. 8, 12 at a later stage during fabrication in accordance with one embodiment. FIG. 14 is a cross-sectional view of extended landing pad substrate package 200 of FIG. 13 at a later stage during fabrication in accordance with one embodiment.

Referring now to FIGS. 1, 13 and 14 together, from strip primary resist and second resist operation 116 and strip resist operation 126, flow moves to a laminate upper and lower circuit patterns to dielectric layer operation 128. In laminate upper and lower circuit patterns to dielectric layer operation 128, upper circuit pattern 1234 and lower circuit pattern 834 are laminated to a dielectric layer 1340.

Dielectric layer 1340 includes an upper, e.g., first, surface 1340U and an opposite lower, e.g., second, surface 1340L. Upper circuit pattern 1234 of upper circuit pattern carrier structure 900 (which has been inverted from the view of FIG. 12) is laminated into upper surface 1340U of dielectric layer 1340. Similarly, lower circuit pattern 834 of lower circuit pattern carrier structure 836 is laminated into lower surface 1340L of dielectric layer 1340.

In one embodiment, upper circuit pattern carrier structure 900 and lower circuit pattern carrier structure 836 are simultaneously pressed into dielectric layer 1340 as indicated by the arrows 1342 in FIG. 13 while the assembly is heated. This causes dielectric layer 1340 to flow around upper circuit pattern 1234 and lower circuit pattern 834 and to seed layers 202. Accordingly, upper circuit pattern 1234 is embedded within upper surface 1340U of dielectric layer 1340 and lower circuit pattern 834 is embedded within lower surface 1340L of dielectric layer 1340 as illustrated in FIG. 14.

In accordance with one embodiment, thickness T3 of upper circuit pattern 1234 is approximately equal to thickness T1 of traces 418. However, in other embodiments, thickness T3 of upper circuit pattern 1234 is greater than or less than thickness T1 of traces 418.

FIG. 15 is a cross-sectional view of extended landing pad substrate package 200 of FIG. 14 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 1, 14 and 15 together, from laminate upper and lower circuit patterns to dielectric layer operation 128, flow moves to a remove carriers operation 130. In remove carriers operation 130, carriers 204 of circuit pattern carrier structures 900, 836 are removed. Illustratively, carriers 204 are removed by etching, mechanical grinding, and/or peeling.

From remove carriers operation 130, flow moves to a remove seed layers operation 132. In remove seed layers operation 132, seed layers 202 of circuit pattern carrier structures 900, 836 are removed. Illustratively, seed layers 202 are removed by etching and/or mechanical grinding.

As illustrated in FIG. 15, after removal of seed layers 202, upper surface 1340U, upper circuit pattern 1234, lower surface 1340L, and lower circuit pattern 834 are exposed.

From remove seed layers operation 132, flow moves to a form blind via apertures operation 134. In form blind via apertures operation 134, blind via apertures 1544 are formed, e.g., using laser-ablation. Blind via apertures 1544 extend through upper circuit pattern 1234 and dielectric layer 1340 and to extended landing pads 732 of lower circuit pattern 834. Blind via apertures 1544 expose extended landing pads 732 but do not extend through extended landing pads 732.

As extended landing pads 732 have an increased thickness T2 as compared to thickness T1 of traces 418 of lower circuit pattern 834, the length L1 of blind via apertures 1544 is minimized. Length L1, sometimes called a first distance, is the distance between extended landing pads 732 and upper surface 1340U of dielectric layer 1340. In contrast, a length L2 greater than length L1 exists between traces 418 and upper surface 1340U of dielectric layer 1340. More particularly, length L2, sometimes called a second distance, is the distance between traces 418 and upper surface 1340U of dielectric layer 1340.

Further, blind via apertures 1544 have a first width W3 at upper surface 1340U of dielectric layer 1340 and a second width W4 at extended landing pads 732. As illustrated, blind via apertures 1544 taper from width W3 at upper surface 1340U of dielectric layer 1340 to width W4 at extended landing pads 732, width W3 being greater than width W4.

As those of skill in the art will understand in light of this disclosure, blind via apertures have an aspect ratio, i.e., a length to width ratio, due to the laser-ablation process used to form the blind via aperture. For example, the aspect ratio of blind via apertures 1544 is length L1 divided by width W3 (L1/W3).

Accordingly, as the length of blind via apertures decreases, the resulting width of the blind via apertures also decreases. As discussed above, the length L1 of blind via apertures 1544 is minimized due to the increased thickness T2 of extended landing pads 732 as compared to thickness T1 of traces 418. Accordingly, the width W3 of blind via apertures 1544 at upper surface 1340U of dielectric layer 1340 is minimized. Accordingly, extremely small blind via apertures 1544 are formed even when dielectric layer 1340 is relatively thick. This enables upper circuit pattern 1234 to be formed with minimum feature size.

In one embodiment, by minimizing length L1 of blind via apertures 1544, tolerance in the alignment between blind via apertures 1544 and extended landing pads 732 is minimized. This enables the width of extended landing pads 732 in a direction parallel to lower surface 1340L of dielectric layer 1340 to be minimized. This, in turn, enables lower circuit pattern 834 to be formed with minimum feature size.

In one embodiment, by minimizing length L1 of blind via apertures 1544, the time required to form blind via apertures 1544 is minimized thus minimizing the cost of the blind via laser-ablation process and thus of extended landing pad substrate package 200.

FIG. 16 is a cross-sectional view of extended landing pad substrate package 200 of FIG. 15 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 1, 15 and 16 together, from form blind via apertures operation 134, flow moves to a form blind vias operation 136. In form blind vias operation 136, blind vias 1646 are formed within blind via apertures 1544. More particularly, blind via apertures 1544 are filled with electrically conductive material, e.g., by plating a blind via metal or applying an electrically conductive epoxy, to form blind vias 1646.

Blind vias 1646 extend through upper circuit pattern 1234 and dielectric layer 1340 and to extended landing pads 732 of lower circuit pattern 834. Accordingly, upper circuit pattern 1234 is electrically connected to lower circuit pattern 834 through dielectric layer 1340 by blind vias 1646. Blind vias 1646 are formed within blind via apertures 1544 and thus the above discussion of blind via apertures 1544 and the relative dimensions thereof are equally applicable to blind vias 1646.

Extended landing pad substrate package 200 at the stage illustrated in FIG. 16 is sometimes referred to as an extended landing pad substrate 1648. Extended landing pad substrate 1648 includes dielectric layer 1340, upper circuit pattern 1234 embedded within upper surface 1340U of dielectric layer 1340, lower circuit pattern 834 embedded within lower surface 1340L of dielectric layer 1340, and blind vias 1646 electrically connecting upper and lower circuit patterns 1234, 834 through dielectric layer 1340. Extending landing pad substrate 1648 includes an upper, e.g., first surface 1648U and an opposite lower, e.g., second, surface 1648L.

FIG. 17 is a cross-sectional view of extended landing pad substrate package 200 of FIG. 16 at a later stage during fabrication in accordance with one embodiment. Referring now to FIGS. 1 and 17 together, from form blind vias operation 136, flow moves to a mount electronic component(s) operation 138. In mount electronic component(s) operation 138, at least one electronic component 1750 is mounted to extended landing pad substrate 1648.

Electronic component 1750 is an integrated circuit chip, i.e., an active component, in accordance with this embodiment. However, in other embodiments, electronic component 1750 is a passive component, e.g., a capacitor, resistor or inductor.

In the embodiment illustrated in FIG. 17, electronic component 1750 is mounted in a wire bond configuration. More particularly, electronic component 1750 includes an inactive surface 17501 mounted to upper surface 1648U of extended landing pad substrate 1648 with an adhesive 1752, sometimes called a die attach adhesive. Bond pads 1754 on an active surface 1750A of electronic component 1750 are electrically connected to upper circuit pattern 1234 by bond wires 1756. Optionally, a package body 1758, e.g., an encapsulant, molding compound, or other dielectric material, is formed to encapsulate and protect electronic component 1750 and bond wires 1756.

From mount electronic component(s) operation 138, flow moves, optionally, to a form interconnection balls operation 140. In form interconnection balls operation 140, interconnection balls 1760, e.g., solder balls, are formed on lower circuit pattern 834. Interconnection balls 1760, e.g., a ball grid array, are used to electrically interconnect and mount extended landing pad substrate package 200 to a larger substrate such as a printed circuit motherboard. However, in another embodiment, interconnection balls 1760 are not formed and thus form interconnection balls operation 140 is an optional operation.

FIG. 18 is a cross-sectional view of extended landing pad substrate package 200 of FIG. 16 at a later stage during fabrication in accordance with another embodiment. Referring now to FIGS. 1 and 18 together, from form blind vias operation 136, flow moves to mount electronic component(s) operation 138. In mount electronic component(s) operation 138, at least one electronic component 1850 is mounted to extended landing pad substrate 1648.

Electronic component 1850 is an integrated circuit chip, i.e., an active component, in accordance with this embodiment. However, in other embodiments, electronic component 1850 is a passive component, e.g., a capacitor, resistor or inductor.

In the embodiment illustrated in FIG. 18, electronic component 1850 is mounted in a flip chip configuration. More particularly, electronic component 1850 includes an inactive surface 18501 and an opposite active surface 1850A. Bond pads 1854 on active surface 1850A of electronic component 1850 are physically and electrically connected to upper circuit pattern 1234 by flip chip bumps 1856, e.g., solder bumps. Optionally, an underfill material 1858 is formed between upper surface 1648U of extended landing pad substrate 1648 and active surface 1850A of electronic component 1850 to encapsulate and protect flip chip bumps 1856.

From mount electronic component(s) operation 138, flow moves, optionally, to form interconnection balls operation 140. In form interconnection balls operation 140, interconnection balls 1860, e.g., solder balls, are formed on lower circuit pattern 834. Interconnection balls 1860, e.g., a ball grid array, are used to electrically interconnect and mount extended landing pad substrate package 200 to a larger substrate such as a printed circuit motherboard. However, in another embodiment, interconnection balls 1860 are not formed and thus form interconnection balls operation 140 is an optional operation.

Although formation of an individual extended landing pad substrate package 200 is described above, in other embodiments, a plurality of extended landing pad substrate package 200 are formed simultaneously in an array or strip using extended landing pad substrate package formation method 100 as described above. The array or strip is singulated to singulate extended landing pad substrate packages 200 from one another.

The drawings and the forgoing description gave examples of the present invention. The scope of the present invention, however, is by no means limited by these specific examples. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of the invention is at least as broad as given by the following claims.

Claims

1. A method of forming an extended landing pad substrate package, the method comprising: plating a primary conductor layer, the primary conductor layer comprising: a trace having a first thickness; andan extended landing pad foundation portion having the first thickness;selectively plating an extension conductor layer on the extended landing pad foundation portion but not on the trace, the extension conductor layer comprising: an extended landing pad extension portion on the extended landing pad foundation portion, the extended landing pad extension portion and the extended landing pad foundation portion forming an extended landing pad having a second thickness greater than the first thickness;laminating a first circuit pattern comprising the trace and the extended landing pad into a dielectric layer; andforming a blind via aperture extending through the dielectric layer and to the extended landing pad.

2. The method of claim 1 comprising forming a seed layer on a carrier, and wherein said plating a primary conductor layer comprises: applying a primary resist to the seed layer;patterning the primary resist to define a circuit pattern artifact in the primary resist; andat least partially filling the circuit pattern artifact with the primary conductor layer.

3. The method of claim 1 wherein said laminating comprises embedding the first circuit pattern into a first surface of the dielectric layer, the method comprising laminating a second circuit pattern into a second surface of the dielectric layer, the blind via aperture extending from the second surface of the dielectric layer to the extended landing pad.

4. The method of claim 3 comprising forming a blind via in the blind via aperture, the blind via electrically connecting the first circuit pattern and the second circuit pattern.

5. A method of forming an extended landing pad substrate package, the method comprising: forming a seed layer on a carrier;plating a primary conductor layer, the primary conductor layer comprising: a trace having a first thickness; andan extended landing pad foundation portion having the first thickness;selectively plating an extended landing pad extension portion on the extended landing pad foundation portion, the extended landing pad extension portion and the extended landing pad foundation portion forming an extended landing pad having a second thickness greater than the first thickness;laminating a first circuit pattern comprising the trace and the extended landing pad into a dielectric layer; andforming a blind via aperture extending through the dielectric layer and to the extended landing pad,wherein said plating a primary conductor layer comprises: applying a primary resist to the seed layer;patterning the primary resist to define a circuit pattern artifact in the primary resist; andat least partially filling the circuit pattern artifact with the primary conductor layer, andwherein said selectively plating comprises: applying a secondary resist to the primary resist and to the primary conductor layer;patterning the secondary resist to expose at least a portion of the extended landing pad foundation portion; andplating a secondary conductor layer on the exposed extended landing pad foundation portion, wherein the secondary conductor layer forms the extended landing pad extension portion.

6. The method of claim 5 comprising stripping the primary resist and the secondary resist.

7. A method of forming an extended landing pad substrate package, the method comprising: applying a primary mask;patterning the primary mask to define a circuit pattern artifact;plating a primary conductor layer in the circuit pattern artifact, the primary conductor layer comprising: a trace having a first thickness; andan extended landing pad foundation having the first thickness;applying a secondary mask to the primary mask and to the primary conductor layer;patterning the secondary mask to define an extended landing pad overlay pattern artifact that exposes at least a portion of the extended landing pad foundation;selectively plating an extended landing pad extension on the extended landing pad foundation through the extended landing pad overlay pattern artifact, where an extended landing pad comprising the extended landing pad foundation and the extended landing pad extension has a second thickness greater than the first thickness;removing the primary and secondary masks;embedding a first circuit pattern comprising the trace and the extended landing pad in a dielectric layer; andforming a blind via aperture extending through the dielectric layer and to the extended landing pad.

8. The method of claim 7, wherein the circuit pattern artifact comprises an extended landing pad pattern artifact in which the extended landing pad foundation is plated, and the extended landing pad overlay pattern artifact has a different width than the extended landing pad pattern artifact.

9. The method of claim 8, wherein the extended landing pad overlay pattern artifact has a greater width than the extended landing pad pattern artifact.

10. The method of claim 7, wherein the extended landing pad foundation comprises a vertical side, and the extended landing pad extension comprises a vertical side.

11. The method of claim 10, wherein the respective vertical sides of the extended landing pad foundation and the extended landing pad extension are aligned.

12. The method of claim 7, wherein said forming a blind via aperture comprises forming the blind via aperture with sloped sides.

13. The method of claim 7, comprising coupling a conductive ball to the extended landing pad foundation.

14. The method of claim 13, comprising directly attaching the conductive ball to the extended landing pad foundation.

15. The method of claim 7, wherein said laminating comprises pressing the first circuit pattern into the dielectric layer.

16. A method of forming an extended landing pad substrate package, the method comprising: applying a primary mask;patterning the primary mask to define a circuit pattern artifact;plating a primary conductor layer in the circuit pattern artifact, the primary conductor layer comprising: a trace having a first thickness; andan extended landing pad foundation having the first thickness;applying a secondary mask to the primary mask and to the primary conductor layer;patterning the secondary mask to define an extended landing pad overlay pattern artifact that exposes at least a portion of the extended landing pad foundation;selectively plating an extended landing pad extension on the extended landing pad foundation through the extended landing pad overlay pattern artifact, where an extended landing pad comprising the extended landing pad foundation and the extended landing pad extension has a second thickness greater than the first thickness;removing the primary and secondary masks;embedding a first circuit pattern comprising the trace and the extended landing pad in a first surface of a dielectric layer;forming a blind via aperture extending through the dielectric layer and to the extended landing pad; andembedding a second circuit pattern having a third thickness in a second surface of the dielectric layer, where the second thickness of the extended landing pad is greater than the third thickness of the second circuit pattern.

17. The method of claim 16, wherein the second thickness of the extended landing pad is at least two times greater than the third thickness of the second circuit pattern.

18. The method of claim 17, wherein the second thickness of the extended landing pad is at most three times greater than the third thickness of the second circuit pattern.

19. The method of claim 16, wherein said embedding a first circuit pattern comprises pressing the first circuit pattern into the dielectric layer.

20. The method of claim 19, wherein said embedding a second circuit pattern comprises pressing the second circuit pattern into the dielectric layer simultaneously with said pressing the first circuit pattern into the dielectric layer.