This application claims priority to parent application U.S. Ser. No. 08/580,658 (now U.S. Pat. No. 5,790,830), filed Dec. 29, 1995 and entitled "Extracting Accurate and Efficient Timing Models of Latch-Based Designs."
Number | Name | Date | Kind |
---|---|---|---|
4590581 | Widdoes, Jr. | May 1986 | |
4829446 | Draney | May 1989 | |
5084824 | Lam et al. | Jan 1992 | |
5095454 | Huang | Mar 1992 | |
5111413 | Lazansky et al. | May 1992 | |
5259006 | Price et al. | Nov 1993 | |
5278769 | Bair et al. | Jan 1994 | |
5377122 | Werner et al. | Dec 1994 | |
5452225 | Hammer | Sep 1995 | |
5517136 | Harris et al. | May 1996 | |
5544066 | Rostoker et al. | Aug 1996 | |
5555187 | Spyrou | Sep 1996 | |
5555201 | Dangelo et al. | Sep 1996 | |
5651012 | Jone, Jr. | Jul 1997 | |
5740347 | Avidan | Apr 1998 | |
5790830 | Segal | Aug 1998 |
Entry |
---|
Brian Ebert et al., "SeeSaw: A Verilog Synthesis Viewer," 2nd Annual International Verilog HDL Conference. Design Excellence for Today and Tomorrow; Santa Clara, CA Mar. 22, 1993, pp. 55-60. |
Slides Presented to LSI Logic Corp. Technical Personnel on Jun. 7, 1995 and Aug. 23, 1995, pp. 1-7 and pp. 1-17. |
Burks et al "Indentification of Critical Paths in Circuits With Level-Sensitive Latches," IEEE, pp. 137-141, Nov. 1992. |
Microsoft Press, Computer Dictionary second edition, p. 233, 1994. |
Lee et al "A Timing Analysis Algorithm for Circuits With Level-Sensitive Latches," ACM, pp. 743-748, Jan. 1994. |