Claims
- 1. A method of fabricating a molecular electronic device, comprising:providing a barrier layer to protect a molecular layer sandwiched between a bottom wire layer and a top wire layer from degradation during patterning of the top wire layer, wherein the molecular layer and the top wire layer have a combined thickness that is less than the barrier layer in a region defining the molecular electronic device.
- 2. The method of claim 1, wherein the top wire layer is patterned by disposing a lift-off layer over the barrier layer, disposing an electrically conductive layer over the molecular layer and the lift-off layer, and dissolving the lift-off layer.
- 3. The method of claim 2, wherein the lift-off layer has a different solubility characteristic than the barrier layer.
- 4. The method of claim 3, wherein the lift-off layer is dissolved with a solvent with respect to which the barrier layer is substantially insoluble.
- 5. The method of claim 2, wherein the lift-off layer comprises a polymer and the barrier layer comprises a different polymer.
- 6. The method of claim 5, wherein the lift-off layer comprises PMMA and the barrier layer comprises PDMS.
- 7. The method of claim 6, wherein the lift-off layer is dissolved with acetone.
- 8. The method of claim 2, wherein the lift-off layer comprises a polymer and the barrier layer comprises an inorganic electrical insulator.
- 9. The method of claim 1, wherein the barrier layer comprises an electrical insulator.
- 10. The method of claim 9, wherein the barrier layer comprises a polymer.
- 11. The method of claim 10, wherein the barrier layer comprises PDMS.
- 12. The method of claim 9, wherein the barrier layer comprises an inorganic electrical insulator.
- 13. A method of fabricating a molecular electronic device, comprising:disposing a patterned bottom wire layer over a substrate; disposing over the patterned bottom wire layer a composite layer including a lift-off layer and an underlying barrier layer, the composite layer being patterned to define a device region in which the bottom wire layer is exposed through the lift-off layer and the barrier layer; disposing over the patterned composite layer and the exposed bottom wire layer a molecular layer and an overlying top wire layer with a combined thickness in the device region less than the barrier layer defining the device region; and patterning the top wire layer by dissolving the lift-off layer with a solvent with respect to which the barrier layer is substantially insoluble.
- 14. The method of claim 13, wherein the lift-off layer comprises a polymer and the barrier layer comprises a different polymer.
- 15. The method of claim 14, wherein the lift-off layer comprises PMMA and the barrier layer comprises PDMS.
- 16. The method of claim 13, wherein the lift-off layer comprises a polymer and the barrier layer comprises an inorganic electrical insulator.
- 17. The method of claim 13, wherein the lift-off layer is dissolved with acetone.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is related to U.S. application Ser. No. 09/282,048 now U.S. Pat. No. 6,459,095 filed on Mar. 29, 1999, by James R. Heath et al., and entitled “Chemically Synthesized and Assembled Electronic Devices,” which is incorporated herein by reference.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
6128214 |
Kuekes et al. |
Oct 2000 |
A |
6198655 |
Heath et al. |
Mar 2001 |
B1 |