FABRICATION OF CCD IMAGE SENSORS USING SINGLE LAYER POLYSILICON

Abstract

A method for fabricating CCD imaging structures having single layer polysilicon gates and employing conventional photolithographic techniques and equipment is disclosed. The comprises the steps of providing a silicon substrate; growing a dielectric layer substantially overlying the silicon substrate; depositing a first layer of polysilicon substantially overlaying the dielectric layer; creating a plurality of polysilicon gates and inter-gate gaps from the first layer of polysilicon, each of plurality of the polysilicon gates having a predetermined line width, each pair of the plurality of polysilicon gates having a predetermined inter-gate gap; depositing a second layer of polysilicon of a predetermined thickness substantially overlaying the defined plurality of polysilicon gates and the inter-gate gaps, the predetermined thickness of the second layer of polysilicon being about one half of the predetermined inter-gate gap thickness minus a desired inter-gap thickness; removing at least a portion of the second layer of polysilicon so as to define the plurality of polysilicon gates having the desired inter-gap thickness.

Description

SUMMARY DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a conventional three phase CCD imaging structure with overlapping gates manufactured using conventional photolithographic techniques known in the prior art;

FIG. 2 is cross-sectional view of a CCD imaging structure after the deposition of a layer of polysilicon, the layer having been etched to define poly gates with predetermined inter-gate gaps, constructed using conventional photolithographic techniques according to an embodiment of the present invention;

FIG. 3 is a cross-sectional view of the CCD imaging structure of FIG. 2 after the deposition of a layer of an additional amount of polysilicon deposited over defined polysilicon gates so as to reduce the gap between the gates; and

FIG. 4 is a cross-sectional view of the final CCD imaging structure of the present invention having single layer polysilicon gates with desired predetermined inter-gate gap size.

DETAILED DESCRIPTION OF THE INVENTION

The following embodiments are intended as exemplary, and not limiting. In keeping with common practice, figures are not necessarily drawn to scale.

The steps for manufacturing a CCD imaging structure according to an embodiment of the present invention are depicted in FIGS. 2-4. In FIG. 2, the manufacture of an illustrative CCD imager 24 begins with a silicon substrate 26 having a generally flat active surface 28. A layer of silicon dioxide (dielectric) 30 of a predetermined thickness is grown substantially overlaying the surface 28. By growing the dielectric layer 30, what is meant is that certain species such as oxygen or steam are passed into a chamber (not shown) containing the silicon substrate 26. Oxygen atoms react with the active surface 28 of the substrate 26 so as to grow the layer of silicon dioxide 30. In a second manufacturing step, a layer of polysilicon (not shown) of a predetermined thickness, preferably about 0.5 um, is deposited substantially overlying the layer of silicon dioxide 30. Using standard photolithographic techniques and equipment, the 0.5 um of polysilicon is anisotropically etched to define a plurality of polysilicon gates 32, wherein the gates 32 can have line widths as defined by CCD structure requirement, which can range anywhere from 0.5 um to 12 um. Inter-gate gaps 34 having a predetermined width between the gates 32 are also defined by photolithography and anisotropic etching. In a preferred embodiment, these inter-gate gaps have a width of between about 0.3 um and 2.3 um. This can be achieved by conventional photolithographic tools

Referring now to FIG. 3, an additional layer of polysilicon 36 is deposited substantially overlaying the defined polysilicon gates 32 so as to reduce the gaps between the polysilicon gates 32. This additional deposition layer 36 has a predetermined thickness which is about one half the thickness needed to decrease inter gate gaps to a desired width. In a preferred embodiment, wherein the desired inter-gate thickness is about 0.2 um, and the inter-gate thickness defined by photolithographic process via anisotropic etching is about 0.8 um, the thickness of the additional deposition layer 36 is about 0.3 um. Note in FIG. 3 that the additional deposition layer 36 conforms to all surfaces so that the polysilicon gates 32 are temporarily thicker than desired and there is no exposed oxide layer 30 in the inter-gate gaps 34, which are also reduced in height and width.

In order to render the polysilicon more conductive for the addition of electrodes, the additional deposition layer 36 and the polysilicon gates 32 can be doped to a predetermined desired conductivity. In a preferred embodiment, the additional deposition layer 30 and the polysilicon gates 32 are heavily doped to produce an n+ type or p+ type conductive material. Doping can be effected by diffusion of phosphorus atoms via phosphene gas. In other embodiments, doping can be achieved by ion implantation.

Referring now to FIG. 5, the polysilicon gates 32 with desired inter-gate gaps 34 are defined by an anisotropic etching step. In a preferred embodiment, the inter-gate gaps 34 are now about 0.2 um in width. The polysilicon gates 32 can be isolated electrically from each other by the deposition of an dielectric layer 38 before the addition of electrical contacts (not shown).

While the preferred embodiment of the present invention has been described in terms of the deposition of polysilicon to create single-layer polysilicon gates, in other embodiments, the technique of the present invention is suitable for creating single layer gates made from other conductive materials, such as metals.

The present invention has several advantages over the prior art methods of manufacturing CCD imager structures and the resulting devices. The present invention has fewer processing steps than in a multi-layer polysilicon manufacturing method. Fewer steps translates lower cycle time, higher yields, and lower manufacturing costs. A second advantage of the present invention is the resulting device has lower susceptibility to ESD damage. Front side non-pattern polysilicon and back side polysilicon needs to be removed in both the process of the present invention and in a multi-layer polysilicon process. The back side polysilicon is removed using a plasma etch process, which subjects a device to ionizing radiation. In a multi-layer polysilicon process, when the poly-2 layer on the back side is removed, there still exists a poly-1 layer pattern of conductive lines on the front side. When the poly-3 layer on the back side is removed, poly-1 and poly-2 layers are already patterned on the front side. These patterned layers are susceptible to ESD damage during a backside poly-removal operation using a plasma etch. In the present invention, there is only one layer of polysilicon which needs to be removed and there are no lines of conductive patterns on the front side during the backside poly removals, and therefore there is no threat of ESD damage.

A third advantage is the elimination of polysilicon edge lifting during manufacturing, resulting in higher operating clock voltages. As discussed above, in the conventional multi-layer polysilicon gate manufacturing process, every time a poly-gate is defined, the next step is to grow a channel oxide. For example, after a poly-1 gate is defined, there will be an oxide grown on top of the poly-gate, the side wall of the poly-gate, and the space between poly-gates. Since polysilicon is made of several grains, the silicon oxide grows under the edge of the poly-gate and lifts the entire grain structure. A sidewall chunk of grain begins to lift up. When lifted, the resulting inter-gate gap is not very uniform, so that there will be regions where the poly-gate gaps are narrower than expected, and regions where the gaps are larger than expected., i.e., different from the assumed predetermined gap between the poly-gates. In regions where the oxide thickness is smaller than expected, dielectric breakdown happens at lower applied gate voltages. Because of this, the operation of multiple poly-gate structures are restricted to lower than optimal clock voltages. The single poly-gate structure of the present invention is not susceptible to edge lifting, so that it may be operated at higher clocking voltages which allows for deeper potential wells and therefore greater charge collection capacity.

A fourth advantage is that the elimination of overlapping polysilicon gates results in lower peripheral capacitance. This enhances the speed of CCD operation. In conventional CCD gates, the there are two sources of capacitance: one is caused by gap between the poly-gates along the side walls and the second is the overlying “overlap” region between one gate and another gate. Overlap capacitance is eliminated with a single poly-gate structure. The reduction of this overlap capacitance will enhance the speed of operation. A fifth advantage is that in a single poly, non-overlapping CCD structure, it is easier to silicide the poly gates, resulting in lower resistivity of at least an order of magnitude.

It is to be understood that the exemplary embodiments are merely illustrative of the invention and that many variations of the above-described embodiments may be devised by one skilled in the art without departing from the scope of the invention. It is therefore intended that all such variations be included within the scope of the following claims and their equivalents.

Claims

1. A method for fabricating CCD imaging structures having single layer polysilicon gates and employing conventional photolithographic techniques and equipment, comprising the steps of: providing a silicon substrate;growing a dielectric layer substantially overlying the silicon substrate;depositing a first layer of polysilicon substantially overlaying the dielectric layer;creating a plurality of polysilicon gates and inter-gate gaps from the first layer of polysilicon, each of plurality of the polysilicon gates having a predetermined line width, each pair of the plurality of polysilicon gates having a predetermined inter-gate gap;depositing a second layer of polysilicon of a predetermined thickness substantially overlaying the defined plurality of polysilicon gates and the inter-gate gaps, the predetermined thickness of the second layer of polysilicon being about one half of the predetermined inter-gate gap thickness minus a desired inter-gap thickness;removing at least a portion of the second layer of polysilicon so as to define the plurality of polysilicon gates having the desired inter-gap thickness.

2. The method of claim 1, wherein the step of defining a plurality of polysilicon gates and inter-gate gaps further comprises the steps of: applying photolithography to the first layer of polysilicon to form a desired gate pattern; andanisotropically etching the first layer of polysilicon to remove at least a portion of the first layer of polysilicon so as to form the polysilicon gates and the inter-gate gaps.

3. The method of claim 2, wherein the step of removing at least a portion of the second layer of polysilicon further comprises the step of anisotropically etching the second layer of polysilicon so as to define the plurality of polysilicon gates having the desired inter-gap thickness.

4. The method of claim 3, further comprising the step of doping the second layer of polysilicon and the first layer of polysilicon.

6. The method of claim 4, wherein the second layer of polysilicon and the first layer of polysilicon are doped with one of n type and p type dopants.

7. The method of claim 4, wherein the second layer of polysilicon and the first layer of polysilicon are doped via diffusion.

8. The method of claim 4, wherein the second layer of polysilicon and the first layer of polysilicon are doped via ion implantation.

9. The method of claim 1, further comprising the step of depositing a dielectric layer substantially overlaying the defined polysilicon gates.

10. The method of claim 8, wherein the dielectric layer substantially overlaying the silicon substrate and the dielectric layer substantially overlaying the re-defined polysilicon gates are made of silicon dioxide.

11. The method of claim 1, wherein the desired inter-gate gap thickness is about 0.2 um.

12. The method of claim 10, wherein the predetermined inter-gate gap of the polysilicon gates is between about 0.3 um and 2.3 um.

13. The method of claim 11, wherein the predetermined line width of the polysilicon gates is between about 0.5 um and about 12 um.

14. The method of claim 4, further comprising the step of siliciding the polysilicon gates to increase conductivity.

15. A method for fabricating CCD imaging structures having single layer conductive gates and employing conventional photolithographic techniques and equipment, comprising the steps of: providing a silicon substrate;growing a dielectric layer substantially overlying the silicon substrate;depositing a first layer of a conductive material substantially overlaying the dielectric layer;creating a plurality of conductive gates and inter-gate gaps from the first layer of polysilicon, each of plurality of the conductive gates having a predetermined line width, each pair of the plurality of conductive gates having a predetermined inter-gate gap;depositing a second layer of the conductive material of a predetermined thickness substantially overlaying the defined plurality of conductive gates and the inter-gate gaps, the predetermined thickness of the second layer of conductive material being about one half of the predetermined inter-gate gap thickness minus a desired inter-gap thickness;removing at least a portion of the second layer of conductive material so as to define the plurality of conductive gates having the desired inter-gap thickness.

16. The method of claim 15, wherein the conductive material is metal.

17. The method of claim 15, wherein the step of defining a plurality of conductive gates and inter-gate gaps further comprises the steps of: applying photolithography to the first layer of conductive material to form a desired gate pattern; andanisotropically etching the first layer of conductive material to remove at least a portion of the first layer of conductive material so as to form the conductive gates and the inter-gate gaps.

18. The method of claim 17, wherein the step of removing at least a portion of the second layer of conductive material further comprises the step of anisotropically etching the second layer of conductive material so as to define the plurality of conductive gates having the desired inter-gap thickness.