The embodiments provided herein relate to computational lithography technology, and more specifically to unit cell extraction technology in computational lithography.
In manufacturing processes of integrated circuits (ICs), computational lithography is utilized to improve yields from a design layout of an IC circuit. The ability to perform computational analysis of IC circuit layouts in computationally efficient ways is becoming increasingly important.
In some embodiments, a method of feature-based cell extraction comprises obtaining data representative of a layout, wherein the layout includes a pattern comprising oblique angle features, extracting unit cells from the pattern region comprising oblique angle features, identifying, using the unit cells, a set of regions of the layout matching the unit cells, and
In some embodiments a system comprising a memory storing a set of instructions and at least one processor configured to execute the set of instructions to cause the system to perform obtaining data representative of a layout, wherein the layout includes a pattern comprising oblique angle features or comprising no vertices of features, identifying, using the unit cells, a set of regions of the layout matching the unit cells, and generating, using the unit cells, a hierarchy for the set of regions. The at least one processor configured to execute the set of instructions can cause the system to further perform extracting unit cells is based on structures of the pattern region comprising oblique angle features, determining a feature slope in the pattern region, determining a horizontal or a vertical pitch of structures in the pattern region, constructing a unit cell using the horizontal and vertical pitch, wherein the top and bottom boundaries of the unit cell are defined by the horizontal pitch, the left and right boundaries of the unit cell are defined by the vertical pitch, the location of the unit cell is based on the beginning point of the horizontal or vertical pitch. The at least one processor configured to execute the set of instructions can cause the system to further perform determining a line-space feature of structures in the pattern region, identifying the line-space feature, wherein identifying the line-space feature comprises, identifying segments crossing the pattern region, determining coordinates of locations where the segment intersects with structures on the layout, and determining an anchor point for the segment based on the line-space feature. The at least one processor configured to execute the set of instructions can cause the system to further perform constructing a unit cell using the line-space feature, wherein the top and bottom boundaries of the unit cell are defined by the line-space feature and the location of the unit cell is based on the anchor point for the segment. In some embodiments The at least one processor configured to execute the set of instructions can cause the system to further perform storing, the unit cell in an associative data structure, wherein a key for the associative data structure is a feature of the pattern region. Identifying, using the unit cells, a set of regions of the layout matching the unit cells, can include identifying a feature of the pattern region, using the feature as a key, retrieving a unit cell from the associative data structure, and matching portions of the pattern region using the retrieved unit cell. In some embodiments The at least one processor configured to execute the set of instructions can cause the system to further perform optimizing the unit cell distribution on the set of regions using a linear optimization function wherein the linear optimization function maximizes the number of unit cells distributed across the set of regions such that the distribution in each region of the set of regions and optimizing the number of unit cells distributed across part of the region and maintaining block level symmetry for the remaining part of the region. The at least one processor configured to execute the set of instructions can cause the system to further perform merging the extracted unit cells and removing duplicate unit cells. In some embodiments the hierarchy is in Graphic Database System (GDS) format, Graphic Database System II (GDS II) format, Open Artwork System Interchange Standard (OASIS) format, or Caltech Intermediate Format (CIF) and the hierarchy is provided for use in at least one of modeling, optical proximity correction (OPC), defect inspection, defect prediction, or source mask optimization (SMO).
In some embodiments, a non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of a computing device can cause the computing device to perform a method of feature extraction for identifying a pattern, the method comprising obtaining data representative of a layout, wherein the layout includes a pattern comprising oblique angle features or no vertices of features, identifying, using the unit cells, a set of regions of the layout matching the unit cells, and generating, using the unit cells, a hierarchy for the set of regions. The method can include extracting unit cells is based on structures of the pattern region comprising oblique angle features, determining a feature slope in the pattern region, determining a horizontal or sa vertical pitch of structures in the pattern region, constructing a unit cell using the horizontal and vertical pitch, wherein the top and bottom boundaries of the unit cell are defined by the horizontal pitch, the left and right boundaries of the unit cell are defined by the vertical pitch, the location of the unit cell is based on the beginning point of the horizontal or vertical pitch. The method can further comprise, determining a line-space feature of structures in the pattern region, identifying the line-space feature, wherein identifying the line-space feature comprises, identifying segments crossing the pattern region, determining coordinates of locations where the segment intersects with structures on the layout, and determining an anchor point for the segment based on the line-space feature. The method can include constructing a unit cell using the line-space feature, wherein the top and bottom boundaries of the unit cell are defined by the line-space feature and the location of the unit cell is based on the anchor point for the segment. In some embodiments the method comprises storing, the unit cell in an associative data structure, wherein a key for the associative data structure is a feature of the pattern region. Identifying, using the unit cells, a set of regions of the layout matching the unit cells, can include identifying a feature of the pattern region, using the feature as a key, retrieving a unit cell from the associative data structure, and matching portions of the pattern region using the retrieved unit cell. In some embodiments the method includes optimizing the unit cell distribution on the set of regions using a linear optimization function wherein the linear optimization function maximizes the number of unit cells distributed across the set of regions such that the distribution in each region of the set of regions and optimizing the number of unit cells distributed across part of the region and maintaining block level symmetry for the remaining part of the region. The method can further comprise merging the extracted unit cells and removing duplicate unit cells. In some embodiments the hierarchy is in Graphic Database System (GDS) format, Graphic Database System II (GDS II) format, Open Artwork System Interchange Standard (OASIS) format, or Caltech Intermediate Format (CIF) and the hierarchy is provided for use in at least one of modeling, optical proximity correction (OPC), defect inspection, defect prediction, or source mask optimization (SMO).
Other advantages of the embodiments of the present disclosure will become apparent from the following description taken in conjunction with the accompanying drawings wherein are set forth, by way of illustration and example, certain embodiments of the present invention.
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise represented. The implementations set forth in the following description of exemplary embodiments do not represent all implementations. Instead, they are merely examples of apparatuses and methods consistent with aspects related to the disclosed embodiments as recited in the appended claims. For example, although some embodiments are described in the context of utilizing electron beams, the disclosure is not so limited. Other types of charged particle beams may be similarly applied. Furthermore, other imaging systems may be used, such as optical imaging, photo detection, x-ray detection, etc.
As the sizes of features and transistors continues to decrease, the ability to faithfully recreate a design layout on a substrate is becoming increasingly difficult. Manufacturing equipment can introduce artifacts or defects when trying to deposit such small features onto the substrate. To account for the physical difficulty of recreating IC layouts at such microscopic scales, IC manufactures rely on techniques such as computational lithography to analyze and modify a design to account for known artifacts of the physical manufacturing process. By adjusting the layout, mask, or other lithography data prior to manufacture to account for known manufacturing artifacts, IC manufacturers can better recreate the originally intended design.
In order to identify what pattern features may result in which physical artifacts, IC manufacturers must utilize enormous data sets to allow for accurate predictions. This can result in computationally expensive techniques that become increasingly complex as IC designs become increasingly complex.
Because of this increased computational complexity and the need for enormous pattern data sets, techniques that can reduce the complexity are important. Because the same feature or group of features may repeat throughout an IC design, effective identification, classification, and selection of those patterns and features can drastically reduce the amount of computation necessary to correct an IC design. To be effective, repeating patterns must be easy to identify, classify, and process. Not all pattern shapes, however, are easily identifiable. In particular, some techniques often rely on distinct vertices, edges, and edge angles to classify and identify features or groups of features. But these techniques are not as effective for pattern features that have no vertices or oblique edge angles. These types of structures are often found in memory (for example, as shown in
According to embodiments of the present disclosure, identification of these types of features can be improved by identifying pattern features (e.g., features shown in
Many downstream applications can utilize the pattern identification and classification consistent with the embodiments described herein, including machine learning based modeling or optical proximity correction (OPC), machine learning based defect inspection and prediction, source mask optimization (SMO) or any other technologies that can select representative patterns for reducing runtime and improving pattern coverage. Some applications intend to reduce the cycle time during standard iteration flow, which may benefit from this invention by applying a representative pattern set instead of full chip in some non-critical cycles. Although embodiments disclosed herein may be disclosed in relation to OPC, SMO, or other specific techniques, the disclosure is not intended to limit the embodiments to those specific applications.
One way to help improve the design pattern layout processing accuracy and quality as well as turn-around time is to perform OPC in a hierarchical mode wherein a hierarchy of pattern features (e.g., the GDS hierarchy) in association with the design pattern layout is used to “re-paste” a previously computed OPC result or recipe a plurality of times. That is, prior to the “re-pasting”, a certain set of pattern features of a design pattern layout can have been processed with one or more optical proximity corrections to obtain an OPC result for that set of pattern features or can have been analyzed to identify specific features for modification or addition by an OPC process to obtain an OPC recipe. The design pattern layout hierarchy can then be scanned for the occurrences of that set of pattern features and then, for each occurrence, the OPC result for that set of pattern features can be inserted into the design pattern layout or the OPC recipe. Thus, the efficiency of OPC processing can be improved because OPC processing does not need to be performed for all the pattern features. Re-using a previously calculated OPC result or recipe can significantly reduce or eliminate having to perform OPC for the repeated features. Furthermore, because only one instance of a set of pattern regions needs to be analyzed, the accuracy of the analysis can be improved (e.g., by taking a longer time than would otherwise be available). Additionally or alternatively, consistency may be achieved as the “re-pasting” can avoid inconsistent results if the same set of pattern features would yield different optimal proximity corrections. So, advanced OPC can be used while keeping total runtime within specification. Moreover, it can enable more consistent OPC.
Relative dimensions of components in drawings may be exaggerated for clarity. Within the following description of drawings, the same or like reference numbers refer to the same or like components or entities, and only the differences with respect to the individual embodiments are described. As used herein, unless specifically stated otherwise, the term “or” encompasses all possible combinations, except where infeasible. For example, if it is stated that a component may include A or B, then, unless specifically stated otherwise or infeasible, the component may include A, or B, or A and B. As a second example, if it is stated that a component may include A, B, or C, then, unless specifically stated otherwise or infeasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.
In a lithographic projection apparatus, a source provides illumination (i.e., radiation) to a patterning device and projection optics direct and shape the illumination, via the patterning device, onto a substrate. The projection optics may include at least some of the components 140, 160a, 160b and 160c. An aerial image (AI) is the radiation intensity distribution at substrate level. A resist model can be used to calculate the resist image from the aerial image. The resist model is related only to properties of the resist layer (e.g., effects of chemical processes which occur during exposure, post-exposure bake (PEB) and development). Optical properties of the lithographic projection apparatus (e.g., properties of the illumination, the patterning device, and the projection optics) dictate the aerial image and can be defined in an optical model. Since the patterning device used in the lithographic projection apparatus can be changed, it is desirable to separate the optical properties of the patterning device from the optical properties of the rest of the lithographic projection apparatus including at least the source and the projection optics. Details of techniques and models used to transform a design layout into various lithographic images (e.g., an aerial image, a resist image, etc.), apply OPC using those techniques and models and evaluate performance (e.g., in terms of process window) are described in U.S. Patent Application Publication Nos. US 2008-0301620, 2007-0050749, 2007-0031745, 2008-0309897, 2010-0162197, and 2010-0180251, the disclosure of each of which is hereby incorporated by reference in its entirety.
The patterning device can comprise, or can form, one or more design layouts. The design layout can be generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional design layouts/patterning devices. These rules are set by processing and design limitations. For example, design rules define the space tolerance between devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the devices or lines do not interact with one another in an undesirable way. One or more of the design rule limitations may be referred to as critical dimension (CD). A critical dimension of a device can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed device. Of course, one of the goals in device fabrication is to faithfully reproduce the original design intent on the substrate (via the patterning device).
The term “mask” or “patterning device” as employed in this text may be broadly interpreted as referring to a generic patterning device that can be used to endow an incoming radiation beam with a patterned cross-section, corresponding to a pattern that is to be created in a target portion of the substrate; the term “light valve” can also be used in this context. Besides the classic mask (transmissive or reflective; binary, phase-shifting, hybrid, etc.), examples of other such patterning devices include:
One aspect of understanding a lithographic process is understanding the interaction of the radiation and the patterning device. The electromagnetic field of the radiation after the radiation passes the patterning device may be determined from the electromagnetic field of the radiation before the radiation reaches the patterning device and a function that characterizes the interaction. This function may be referred to as the mask transmission function (which can be used to describe the interaction by a transmissive patterning device and/or a reflective patterning device).
Variables of a patterning process are called “processing variables.” The patterning process may include processes upstream and downstream to the actual transfer of the pattern in a lithography apparatus. A first category can be variables of the lithography apparatus or any other apparatuses used in the lithography process. Examples of this category include variables of the illumination, projection system, substrate stage, etc. of a lithography apparatus. A second category may be variables of one or more procedures performed in the patterning process. Examples of this category include focus control or focus measurement, dose control or dose measurement, bandwidth, exposure duration, development temperature, chemical composition used in development, etc. A third category may be variables of the design layout and its implementation in, or using, a patterning device. Examples of this category can include shapes and/or locations of assist features, adjustments applied by a resolution enhancement technique (RET), CD of mask features, etc. A fourth category can be variables of the substrate. Examples include characteristics of structures under a resist layer, chemical composition and/or physical dimension of the resist layer, etc. A fifth category can be characteristics of temporal variation of one or more variables of the patterning process. Examples of this category include a characteristic of high frequency stage movement (e.g., frequency, amplitude, etc.), high frequency laser bandwidth change (e.g., frequency, amplitude, etc.) and/or high frequency laser wavelength change. These high frequency changes or movements are those above the response time of mechanisms to adjust the underlying variables (e.g., stage position, laser intensity). A sixth category can be characteristics of processes upstream of, or downstream to, pattern transfer in a lithographic apparatus, such as spin coating, post-exposure bake (PEB), development, etching, deposition, doping and/or packaging.
As will be appreciated, many, if not all of these variables, will have an effect on a parameter of the patterning process and often a parameter of interest. Non-limiting examples of parameters of the patterning process may include critical dimension (CD), critical dimension uniformity (CDU), focus, overlay, edge position or placement, sidewall angle, pattern shift, etc. Often, these parameters express an error from a nominal value (e.g., a design value, an average value, etc.). The parameter values may be the values of a characteristic of individual patterns or a statistic (e.g., average, variance, etc.) of the characteristic of a group of patterns.
The values of some or all of the processing variables, or a parameter related thereto, may be determined by a suitable method. For example, the values may be determined from data obtained with various metrology tools (e.g., a substrate metrology tool). The values may be obtained from various sensors or systems of an apparatus in the patterning process (e.g., a sensor, such as a leveling sensor or alignment sensor, of a lithography apparatus, a control system (e.g., a substrate or patterning device table control system) of a lithography apparatus, a sensor in a track tool, etc.). The values may be from an operator of the patterning process.
It is appreciated that the models used or created with system 200 can represent a different patterning process and need not comprise all the models described below. A source model 201 represents optical characteristics (including radiation intensity distribution, bandwidth and/or phase distribution) of the illumination of a patterning device. The source model 201 can represent the optical characteristics of the illumination that include, but not limited to, numerical aperture settings, illumination sigma (σ) settings as well as any particular illumination shape (e.g., off-axis radiation shape such as annular, quadrupole, dipole, etc.), where σ (or sigma) is outer radial extent of the illuminator.
A projection optics model 210 represents optical characteristics (including changes to the radiation intensity distribution or the phase distribution caused by the projection optics) of the projection optics. The projection optics model 210 can represent the optical characteristics of the projection optics, including aberration, distortion, one or more refractive indexes, one or more physical sizes, one or more physical dimensions, etc.
The patterning device/design layout model module 220 captures how the design features are laid out in the pattern of the patterning device and may include a representation of detailed physical properties of the patterning device, as described, for example, in U.S. Pat. No. 7,587,704, which is incorporated by reference in its entirety. In some embodiments, the patterning device/design layout model module 220 represents optical characteristics (including changes to the radiation intensity distribution or the phase distribution caused by a given design layout) of a design layout (e.g., a device design layout corresponding to a feature of an integrated circuit, a memory, an electronic device, etc.), which is the representation of an arrangement of features on or formed by the patterning device. Since the patterning device used in the lithographic projection apparatus can be changed, it is desirable to separate the optical properties of the patterning device from the optical properties of the rest of the lithographic projection apparatus including at least the illumination and the projection optics. The objective of the simulation is often to accurately predict, for example, edge placements and CDs, which can then be compared against the device design. The device design is generally defined as the pre-OPC patterning device layout and can be provided in a standardized digital file format such as GDS II or OASIS.
An aerial image 230 can be simulated from the source model 200, the projection optics model 210 and the patterning device/design layout model 220. An aerial image (AI) is the radiation intensity distribution at substrate level. Optical properties of the lithographic projection apparatus (e.g., properties of the illumination, the patterning device, and the projection optics) dictate the aerial image.
A resist layer on a substrate is exposed by the aerial image and the aerial image is transferred to the resist layer as a latent “resist image” (RI) therein. The resist image (RI) can be defined as a spatial distribution of solubility of the resist in the resist layer. A resist image 250 can be simulated from the aerial image 230 using a resist model 240. The resist model can be used to calculate the resist image from the aerial image, an example of which can be found in U.S. Pat. No. 8,200,468, the disclosure of which is hereby incorporated by reference in its entirety. The resist model typically describes the effects of chemical processes which occur during resist exposure, post exposure bake (PEB) and development, in order to predict, for example, contours of resist features formed on the substrate and so it typically related only to such properties of the resist layer (e.g., effects of chemical processes which occur during exposure, post-exposure bake and development). In some embodiments, the optical properties of the resist layer, e.g., refractive index, film thickness, propagation, and polarization effects—may be captured as part of the projection optics model 210.
The connection between the optical and the resist model is a simulated aerial image intensity within the resist layer, which arises from the projection of radiation onto the substrate, refraction at the resist interface and multiple reflections in the resist film stack. The radiation intensity distribution (aerial image intensity) is turned into a latent “resist image” by absorption of incident energy, which is further modified by diffusion processes and various loading effects. Efficient simulation methods that are fast enough for full-chip applications approximate the realistic 3-dimensional intensity distribution in the resist stack by a 2-dimensional aerial (and resist) image.
In some embodiments, the resist image can be used an input to a post-pattern transfer process model module 260. The post-pattern transfer process model 260 defines performance of one or more post-resist development processes (e.g., etch, development, etc.).
Simulation of the patterning process can, for example, predict contours, CDs, edge placement (e.g., edge placement error), etc. in the resist or etched image. Thus, the objective of the simulation is to accurately predict, for example, edge placement, aerial image intensity slope, or CD, etc. of the printed pattern. These values can be compared against an intended design to, e.g., correct the patterning process, identify where a defect is predicted to occur, etc. The intended design is generally defined as a pre-OPC design layout which can be provided in a standardized digital file format such as GDS II or OASIS or other file format.
Thus, the model formulation describes most, if not all, of the known physics and chemistry of the overall process, and each of the model parameters desirably corresponds to a distinct physical or chemical effect. The model formulation thus sets an upper bound on how well the model can be used to simulate the overall manufacturing process. In order to effectively model the manufacturing process, system 200 can make use of efficient process, such as those disclosed herein, for pattern selection, categorization, and classification. Embodiments described below can provide improved hierarchies for pattern instances for use with computational lithography models described in relation to
In some embodiments, layout 300 can represent the entirety of an IC layout. In other embodiments layout 300 can represent a portion of a larger layout or design. As shown in
As illustrated in
Data input 410 can provide the data stream to unit cell extractor 420. Unit cell extractor 420 can process the input data, identify areas of the pattern having specific pattern features, e.g., DRAM regions of the data stream, and generate unit cells for matching the same pattern throughout the input data stream, input pattern, or input layout. Exemplary pattern features that can be identified by unit cell extractor 420 are shown in
Referring to
Pattern feature 510 can be identified, for example, by unit cell extractor 420 in
Referring to
Referring to
Referring to
Referring to
Referring back to
Pattern searcher 430 can use the stored hashmaps to search the layout or design for additional patterns. For example, the analysis of one DRAM region of a layout can be used to search for additional DRAM like regions of the layout. As pattern searcher 430 processes the layout, it can identify angles in the various DRAM areas of the pattern and use those angles to retrieve feature values from the various hashmaps. Processing the layout in this way can reduce the amount of processing necessary because processing of a single unit cell can be applied to multiple regions of the layout that match the unit cell. As described in relation to
Referring to
Referring back to
In some embodiments, as shown in
Referring to
t·x=s·x+n*dx
t·y=s·y+m*dy
W=N*pitch·x+2(t·x−b·left)
H=M*pitch·y+2(t·y−b·bottom)
In the above equations, “t·x” and “t·y” can represent the beginning coordinates (i.e., the bottom left coordinates) of the coverage area. As shown in
Referring to
In step 1110, system 400 can obtain a layout (e.g., layout 300 of
In step 1120, system 400 can extract unit cells (e.g., unit cell 710 of
In step 1130, system 400 can search a layout to identify candidate regions that appear to share characteristics of DRAM portions of a layout. System 400 can identify regions that include features with no vertices or regions that have features with oblique line angles as DRAM areas of the layout. In some embodiments, the information stored in hashmaps created as part of step 1120 can be retrieved and used to match areas that have the same features and pattern as the previously processed DRAM region. Using this process, system 400 can identify candidate DRAM regions of a layout (e.g., region 810, region 820, and region 830 of
In step 1140, system 400 can generate a hierarchy of unit cells covering the DRAM regions of the layout. System 400 can process each of the DRAM candidate regions using the unit cells created in step 1120. For each region, system 400 can optimize the layout of unit cells on the DRAM region by treating the region as a linear optimization problem, e.g., as described in relation to
In step 1210, system 400 can be provided a layout (e.g., layout 300 of
In step 1220, system 400 can identify pattern features of the DRAM candidate region. For example, system 400 can identify the slope angle, a (e.g., angle 510 of
In step 1230, system 400 can create unit cells (e.g., unit cell 710 of
In step 1240, system 400 can remove duplicate unit cells. System 400 can generate multiple unit cells based on different candidate regions for pattern. In some instances, different pattern regions can result in the same unit cells. Because the same unit cell can be reused, system 400 can remove duplicate unit cells. Additionally, in some embodiments, different pattern regions can be processed by different processes or on distributed computing devices, which can be referred to as “leaf” nodes. In these embodiments, unit cells found by these “leaf” nodes can be provided to a “host” node. In these embodiments, the “host” node is responsible for removing duplicate unit cells that can be provided by different “leaf” nodes. These embodiments allow for processing of method 1200 to be split among distributed computer systems improving the efficiency of the processing.
In some embodiments, step 1210, step 1220, step 1230, and step 1240 can be performed on a leaf node in a distributed computing environment. In these embodiments, the leaf node can provide the output from step 1240 can be provided to a host for further processing. In these embodiments, the host node can perform the remaining steps of method 1200.
In step 1250, system 400 can merge unit cells found by different processes or from processing different sections of a candidate region into a combined data structure. The unit cells being merged can, in some embodiments, originate from different distributed processing systems, or in some embodiments, can originate from different portions of a candidate DRAM region.
In step 1260, system 400 can remove any remaining duplicates from the merged data structure. System 400 can, in step 1270, provide the remaining unit cells to other components or systems for further use.
In some embodiments, step 1250, step 1260, and step 1270 can be performed on a host node in a distributed computing environment. In these embodiments, the host node can receive input from a one or multiple leaf nodes (e.g., after step 1240) and can use that input for processing in step 1250, step 1260, and step 1270.
In step 1310, system 400 can identify segments (e.g., segment 525 or segment 520 of
In step 1320, system 400 can choose, from the segments, a candidate segment (e.g., segment 650 of
In step 1330, system 400 can determine line-space features (e.g., line 533 and space 537 of
In step 1340, after determining the line-space features of the candidate segment, system 400 can identify an anchor point for the candidate segment. The anchor point can be chosen to be the in the middle of the candidate segment shifted to begin at a line feature. The anchor point can be used to identify lines and pattern regions that have the same characteristics as the candidate line.
The steps of method 1400 can be performed by, for example, system 400 of
In step 1410, system 400 can be provided a layout (e.g., layout 300 of
In step 1420, system 400 can identify the regions of the layout that have DRAM characteristics. In some embodiments, system 400 can be provided with the regions (e.g., region 810, region 820, and region 830 of
In step 1430, system 400 can layout unit cells (e.g., unit cells 710 of
In step 1440, system 400 can process the unit cell layout (e.g., the unit cells for areas 1010 and 1020 shown in
In step 1510, system 400 can obtain a layout (e.g., layout 300 of
In step 1520, system 400 can use patch cut information (e.g., layout 800 of
In some embodiments method 1500 can be implemented in a distributed computing environment including leaf and host nodes. In these embodiments, step 1520 can execute on a leaf node. In these embodiments, because the leaf node may not have access to every region of the layout, including regions existing on other sides of patch cut lines, regions transected by a patch cut line can be provided back to a host for processing in step 1540.
As stated above, for regions existing entirely within a patch, system 400 can proceed to step 1530. In step 1530, system 400 can process the regions and generate appropriate unit cells (e.g., as described in relation to
As stated above, for regions transacted by a patch line, system 400 can proceed to step 1540. In step 1540, system 400 can identify the other portions of regions transected by the patch cut lines and merge adjoining regions into a single region. In some embodiments, where method 1500 is implemented in a distributed computing environment that includes a leaf-host architecture, step 1540 can be implemented on the host and can receive regions separated by patch cut lines from different leaf nodes. After merging the regions, in step 1540, system 400 can generate appropriate unit cells (e.g., as described in relation to
In step 1550, system 400 can generate a hierarchy from the unit cell layout (e.g., areas 1010 and areas 1020 of
A non-transitory computer readable medium may be provided that stores instructions for a processor of a controller (e.g., controller 50 of
Embodiments of the present disclosure can be further described by the following clauses.
1. A method of feature-based cell extraction comprising:
2. The method of clause 1, wherein the pattern region comprises oblique angle features.
3. The method of clauses 1 or 2, wherein the pattern region comprises no vertices of features.
4. The method of any of clauses 1-3, further comprising determining a feature slope in the pattern region.
5. The method of any of clauses 1-3, further comprising determining a horizontal or a vertical pitch of structures in the pattern region.
6. The method of clause 5, further comprising:
7. The method of any of clauses 1-3, further comprising determining a line-space feature of structures in the pattern region.
8. The method of clause 7, further comprising identifying the line-space feature, wherein identifying the line-space feature comprises:
9. The method of clause 8, further comprising:
10. The method of any of clauses 1-9, further comprising:
11. The method of clause 10, wherein identifying, using the unit cells, a set of regions of the layout matching the unit cells, further comprises:
12. The method of any of clauses 1-11, further comprising optimizing the unit cell distribution on the set of regions using a linear optimization function.
13. The method of any of clause 12 wherein the linear optimization function comprises:
14. The method of any one of clauses 1-13, wherein the method further comprises:
15. The method of any of clauses 1-14, wherein the hierarchy is in Graphic Database System (GDS) format, Graphic Database System II (GDS II) format, Open Artwork System Interchange Standard (OASIS) format, or Caltech Intermediate Format (CIF).
16. The method of any one of clauses 1-15, wherein the hierarchy is provided for use in at least one of modeling, optical proximity correction (OPC), defect inspection, defect prediction, or source mask optimization (SMO).
17. A system comprising:
18. The system of clause 17, wherein the pattern region comprises oblique angle features.
19. The system of clauses 17 or 18, wherein the pattern region comprises no vertices of features.
20. The system of any of clauses 17-19, wherein the at least one processor is configured to execute the set of instructions to cause the system to further perform determining a feature slope in the pattern region.
21. The system of any of clauses 17-19, wherein the at least one processor is configured to execute the set of instructions to cause the system to further perform determining a horizontal or a vertical pitch of structures in the pattern region.
22. The system of clause 21, wherein the at least one processor is configured to execute the set of instructions to cause the system to further perform:
23. The system of any of clauses 17-19 wherein the at least one processor is configured to execute the set of instructions to cause the system to further perform determining a line-space feature of structures in the pattern region.
24. The system of clause 23, wherein the at least one processor is configured to execute the set of instructions to cause the system to further perform:
25. The system of clause 24, wherein the at least one processor is configured to execute the set of instructions to cause the system to further perform:
26. The system of any of clauses 17-25, wherein the at least one processor is configured to execute the set of instructions to cause the system to further perform:
27. The system of any of clauses 26, wherein the at least one processor is configured to execute the set of instructions to cause the system to further perform:
28. The system of any of clauses 17-27, wherein the at least one processor is configured to execute the set of instructions to cause the system to further perform optimizing the unit cell distribution on the set of regions using a linear optimization function.
29. The system of clause 28, wherein the linear optimization function:
30. The system of any of clauses 17-29, wherein the at least one processor is configured to execute the set of instructions to cause the system to further perform:
31. The system of any of clauses 17-30, wherein the hierarchy is in Graphic Database System (GDS) format, Graphic Database System II (GDS II) format, Open Artwork System Interchange Standard (OASIS) format, or Caltech Intermediate Format (CIF).
32. The system of any of clauses 17-31, wherein the hierarchy is provided for use in at least one of modeling, optical proximity correction (OPC), defect inspection, defect prediction, or source mask optimization (SMO).
33. A non-transitory computer readable medium that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to perform a method of feature extraction for identifying a pattern, the method comprising:
34. The non-transitory computer readable medium of clause 33, wherein the pattern region comprises oblique angle features.
35. The non-transitory computer readable medium of any of clauses 33 or 34, wherein the pattern region comprises no vertices of features.
36. The non-transitory computer readable medium of any of clauses 33-35 that store a set of instructions that is executable by at least one processor of a computing device to cause the computing device to further perform determining a feature slope in the pattern region.
37. The non-transitory computer readable medium of any of clauses 33-35 that store a set of instructions that is executable by at least one processor of a computing device to cause the computing device to further perform determining a horizontal or a vertical pitch of structures in the pattern region.
38. The non-transitory computer readable medium of clause 37 that store a set of instructions that is executable by at least one processor of a computing device to cause the computing device to further perform:
39. The non-transitory computer readable medium of any of clauses 33-35 that store a set of instructions that is executable by at least one processor of a computing device to cause the computing device to further perform determining a line-space feature of structures in the pattern region.
40. The non-transitory computer readable medium of clause 39 that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to further perform identifying the line-space feature, wherein identifying the line-space feature comprises:
41. The non-transitory computer readable medium of clause 40 that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to further perform, further comprising:
42. The non-transitory computer readable medium of any of clauses 33-41 that store a set of instructions that is executable by at least one processor of a computing device to cause the computing device to further perform, further comprising:
43. The non-transitory computer readable medium of clause 42 that stores a set of instructions that is executable by at least one processor of a computing device to cause the computing device to further perform, wherein identifying, using the unit cells, a set of regions of the layout matching the unit cells, further comprises:
44. The non-transitory computer readable medium of any of clauses 33-43 that store a set of instructions that is executable by at least one processor of a computing device to cause the computing device to further perform optimizing the unit cell distribution on the set of regions using a linear optimization function.
45. The non-transitory computer readable medium of clause 44, wherein the linear optimization function:
46. The non-transitory computer readable medium of any of clauses 33-45 that store a set of instructions that is executable by at least one processor of a computing device to cause the computing device to further perform, wherein the method further comprises:
47. The non-transitory computer readable medium of any of clauses 33-46, wherein the hierarchy is in Graphic Database System (GDS) format, Graphic Database System II (GDS II) format, Open Artwork System Interchange Standard (OASIS) format, or Caltech Intermediate Format (CIF).
48. The non-transitory computer readable medium of any of clauses 33-47, wherein the hierarchy is provided for use in at least one of modeling, optical proximity correction (OPC), defect inspection, defect prediction, or source mask optimization (SMO).
The block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer hardware/software products according to various exemplary embodiments of the present disclosure. In this regard, each block in a schematic diagram may represent certain arithmetical or logical operation processing that may be implemented using hardware such as an electronic circuit. Blocks may also represent a module, a segment, or a portion of code that comprises one or more executable instructions for implementing the specified logical functions. It should be understood that in some alternative implementations, functions indicated in a block may occur out of the order noted in the figures. For example, two blocks shown in succession may be executed or implemented substantially concurrently, or two blocks may sometimes be executed in reverse order, depending upon the functionality involved. Some blocks may also be omitted.
It will be appreciated that the embodiments of the present disclosure are not limited to the exact construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof. The present disclosure has been described in connection with various embodiments, other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
The descriptions above are intended to be illustrative, not limiting. Thus, it will be apparent to one skilled in the art that modifications may be made as described without departing from the scope of the claims set out below.
Number | Date | Country | Kind |
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PCT/CN2020/137957 | Dec 2020 | WO | international |
This application claims priority of PCT application PCT/CN2020/137957 which was filed on 21 Dec. 2020, and which is incorporated herein in its entirety by reference.
Filing Document | Filing Date | Country | Kind |
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PCT/EP2021/082880 | 11/24/2021 | WO |