Patent Application
20250151369
The present disclosure relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for a ferroelectric capacitive memory device and methods of forming a structure for a ferroelectric capacitive memory device.
A ferroelectric capacitor consists of a layer of ferroelectric material disposed between a pair of electrodes that can be used to apply a bidirectional electric field. When deployed in a ferroelectric capacitive memory device, a ferroelectric capacitor can be selectively switched by the bidirectional electric field between a high capacitance condition and a low capacitance condition representing different net polarization states of the ferroelectric material. The different capacitance conditions may be used to program the ferroelectric capacitive memory device with non-volatile binary logic states.
Improved structures for a ferroelectric capacitive memory device and methods of forming a structure for a ferroelectric capacitive memory device are needed.
In an embodiment of the invention, a structure for a ferroelectric capacitive memory device is provided. The structure comprises a first electrode including a first doped region in a semiconductor layer and a second doped region in the semiconductor layer, an interconnection that is configured to connect the first doped region to the second doped region, a ferroelectric layer on the semiconductor layer, and a second electrode including a first section and a second section on the ferroelectric layer. The first section of the second electrode comprises a first material with a first work function, and the second section of the second electrode comprises a second material with a second work function that is greater than the first work function of the first material.
In an embodiment of the invention, a method of forming a structure for a ferroelectric capacitive memory device is provided. The method comprises forming a ferroelectric layer on a semiconductor layer, forming a second electrode that includes a first section and a second section on the ferroelectric layer, and forming a first electrode that includes a first doped region in the semiconductor layer and a second doped region in the semiconductor layer. The first section of the second electrode comprises a first material with a first work function, and the second section of the second electrode comprises a second material with a second work function that is greater than the first work function of the first material. The method further comprises forming an interconnection that is configured to connect the first doped region to the second doped region.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description given above and the detailed description given below, serve to explain the embodiments of the invention.
With reference to
A shallow trench isolation region 18 may be formed in the semiconductor layer 12. The shallow trench isolation region 18 may be formed by patterning a shallow trench extending through the semiconductor layer 12 to the dielectric layer 14, depositing a dielectric material, such as silicon dioxide, to fill the shallow trench, and planarizing and/or recessing the deposited dielectric material.
A doped region 30 may be disposed in the semiconductor substrate 16 beneath the dielectric layer 14 and may function as a back gate in the structure 10. The doped region 30 may be formed by introducing a dopant with, for example, ion implantation into the semiconductor substrate 16. A patterned implantation mask may be formed on the top surface of the semiconductor layer 12 to define a selected surface area that is exposed for implantation. The implantation mask may include a layer of an organic photoresist that is applied and patterned to form an opening exposing the selected area on the top surface of the semiconductor layer 12 and determining, at least in part, the location and horizontal dimensions of the doped region 30 in the semiconductor substrate 16. The implantation mask, which is stripped following implantation, has a thickness and stopping power sufficient to block implantation in masked areas. The implantation conditions, such as ion species, dose, and kinetic energy, may be selected to tune the electrical and physical characteristics of the doped region 30. In an embodiment, the doped region 30 may be doped with a concentration of an n-type dopant, such as arsenic or phosphorus, to provide n-type conductivity.
A ferroelectric layer 20 may be formed on the semiconductor layer 12 and shallow trench isolation region 18. The ferroelectric layer 20 may be comprised of a ferroelectric material, such as a high-k dielectric material like hafnium-aluminum oxide, deposited by, for example, atomic layer deposition. The ferroelectric material of the ferroelectric layer 20, which is an electrical insulator, may be crystallized by an anneal following deposition. In an embodiment, the ferroelectric layer 20 may include crystalline grains characterized by an orthorhombic phase that exhibits ferroelectricity. An interfacial layer (not shown) may be disposed between the ferroelectric layer 20 and the semiconductor layer 12 and may comprised of a dielectric material, such as silicon dioxide, that is an electrical insulator and differs in composition from the ferroelectric layer 20. In an embodiment, a uniform thickness of the ferroelectric material of the ferroelectric layer 20 may fully overlap with the entirety of the semiconductor layer 12 and shallow trench isolation region 18.
An electrode layer 22 is disposed on the ferroelectric layer 20. In an embodiment, the electrode layer 22 may directly contact the ferroelectric layer 20. The electrode layer 22, which may be formed by deposition on the ferroelectric layer 20, is comprised of a material having a work function. In an embodiment, the electrode layer 22 may be comprised of polysilicon doped with an n-type dopant. An n-type dopant may be effective to lower the work function of polysilicon relative to intrinsic polysilicon.
With reference to
An electrode layer 24 is disposed in sections on the portions of the ferroelectric layer 20 adjacent to the sidewalls 23, 25 of the patterned electrode layer 22. In an embodiment, the sections of the electrode layer 24 may directly contact the underlying portions of the ferroelectric layer 20 adjacent to the sidewalls 23, 25 of the patterned electrode layer 22. In an embodiment, the electrode layer 24 may be comprised of a material having a work function that is greater than the work function of the electrode layer 22. In an embodiment, the electrode layer 24 may be comprised of polysilicon doped with a p-type dopant. A p-type dopant may be effective to increase the work function of polysilicon relative to intrinsic polysilicon. In an embodiment, the sections of the electrode layer 24 may be formed by conformally depositing a layer of polysilicon and anisotropically etching the deposited layer with, for example, a reactive ion etching process. In an alternative embodiment, the electrode layer 24 may be comprised of p-type polysilicon, titanium nitride, tantalum nitride, aluminum, copper, or a combination of these materials.
With reference to
Each section of the electrode layer 22 is associated with one of the sections of the electrode layer 24 to define electrodes 26, 28. The electrodes 26, 28 are disposed on patterned sections of the ferroelectric layer 20 over different portions of the semiconductor layer 12. In an embodiment, the section of the electrode layer 22 and the section of the electrode layer 24 in each of the electrodes 26, 28 may be juxtaposed with a side-by-side arrangement. In an embodiment, the section of the electrode layer 22 and the section of the electrode layer 24 in each of the electrodes 26, 28 may be in direct contact. In an embodiment, the section of the electrode layer 22 may laterally adjoin the section of the electrode layer 24 in each of the electrodes 26, 28. In an embodiment, the section of the electrode layer 22 and the section of the electrode layer 24 in each of the electrodes 26, 28 may be coextensive.
With reference to
With reference to
The ferroelectric material constituting the ferroelectric layer 20 is characterized by a pair of stable remanent polarization states that are persistent and that can be reversibly varied in response to an electric field applied between the respective electrodes of each ferroelectric capacitive memory device. The pair of stable remanent polarization states represent binary logic states in a ferroelectric capacitive memory device. In one remnant polarization state, the net polarization of the ferroelectric material in the crystalline grains may be oriented parallel to each other, which may provide a low capacitance state. In the other remnant polarization state, the net polarization of the ferroelectric material in the crystalline grains may be oriented anti-parallel to each other, which may provide a high capacitance state. The low and high capacitance states of the remnant polarization states enable the different binary logic states. The back gate provided by the doped region 30 may be biased to enhance the electric field used to provide the different binary logic states.
The hybrid electrodes 26, 28 containing materials of different work function may improve the performance of each ferroelectric capacitive memory device. In that regard, the electrode layer 22 of lower work function may enhance electron injection, especially in combination with additional biasing by the back gate provided by the doped region 30, such that the efficiency of programming the high-capacitance state is enhanced. The electrode layer 24 of higher work function may increase surface accumulation of the doped regions 32, 34 and may increase the threshold voltage, which may significantly increase band-to-band tunneling and/or gate-induced drain leakage and thereby enhance the efficiency of programming the low-capacitance state.
With reference to
The electrode 26 includes one of the sections of the electrode layer 22 and a pair of sections of the electrode layer 24 that are respectively positioned adjacent to the sidewall 23 and the sidewall 27 of the electrode layer 22. The section of the electrode layer 22 of the electrode 26 is laterally disposed between the sections of the electrode layer 24 of the electrode 26. In an embodiment, the section of the electrode layer 22 of the electrode 26 may be coextensive with each section of the electrode layer 24 of the electrode 26. In an embodiment, the sections of the electrode layer 24 of the electrode 26 may be in direct contact with the opposite sidewalls 23 and 27 of the section of the electrode layer 22 of the electrode 26.
The electrode 28 includes one of the sections of the electrode layer 22 and a pair of sections of the electrode layer 24 that are respectively positioned adjacent to the sidewall 25 and the sidewall 29 of the electrode layer 22. The section of the electrode layer 22 of the electrode 28 is laterally disposed between the sections of the electrode layer 24 of the electrode 28. In an embodiment, the section of the electrode layer 22 of the electrode 28 may be coextensive with each section of the electrode layer 24 of the electrode 28. In an embodiment, the sections of the electrode layer 24 of the electrode 28 may be in direct contact with the sidewalls 25 and 29 of the section of the electrode layer 22. In an embodiment, the section of the electrode layer 22 of the electrode 28 may be coextensive with each section of the electrode layer 24 of the electrode 28.
In an embodiment, the sections of the electrode layer 24 may be comprised of a material having a work function that is greater than the work function of the electrode layer 22. In an alternative embodiment, the materials of the sections of the electrode layer 24 and the electrode layer 22 may be swapped.
The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.
References herein to terms modified by language of approximation, such as “about”, “approximately”, and “substantially”, are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate a range of +/−10% of the stated value(s).
References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction in the frame of reference perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction in the frame of reference within the horizontal plane.
A feature “connected” or “coupled” to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to or with another feature if intervening features are absent. A feature may be “indirectly connected” or “indirectly coupled” to or with another feature if at least one intervening feature is present. A feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be “directly on” or in “direct contact” with another feature if intervening features are absent. A feature may be “indirectly on” or in “indirect contact” with another feature if at least one intervening feature is present. Different features may “overlap” if a feature extends over, and covers a part of, another feature.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
