Patent Application
20170345831
Ferroelectric devices (e.g., capacitors and transistors), and methods of forming ferroelectric devices.
Memory is one type of integrated circuitry, and is used in computer systems for storing data. Memory may be fabricated in one or more arrays of individual memory cells. Memory cells may be written to, or read from, using digit lines (which may also be referred to as bitlines, data lines, sense lines, or data/sense lines) and access lines (which may also be referred to as wordlines). The digit lines may conductively interconnect memory cells along columns of the array, and the access lines may conductively interconnect memory cells along rows of the array. Each memory cell may be uniquely addressed through the combination of a digit line and an access line.
Memory cells may be volatile or non-volatile. Non-volatile memory cells can store data for extended periods of time including when the computer is turned off. Volatile memory dissipates and therefore requires being refreshed/rewritten, in many instances multiple times per second. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.
A capacitor is one type of electronic component that may be used in a memory cell. A capacitor has two electrical conductors separated by electrically insulating material. Energy as an electric field may be electrostatically stored within such material. One type of capacitor is a ferroelectric capacitor which has ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarized states and thereby can comprise programmable material of a memory cell. The polarization state of the ferroelectric material can be changed by application of suitable programming voltages, and remains after removal of the programming voltage (at least for a time). Each polarization state has a different charge-stored capacitance from the other, and which ideally can be used to write (i.e., store) and read a memory state without reversing the polarization state until such is desired to be reversed. Less desirable, in some memory having ferroelectric capacitors the act of reading the memory state can reverse the polarization. Accordingly, upon determining the polarization state, a re-write of the memory cell is conducted to put the memory cell into the pre-read state immediately after its determination. Regardless, a memory cell incorporating a ferroelectric capacitor ideally is non-volatile due to the bi-stable characteristics of the ferroelectric material that forms a part of the capacitor. One type of memory cell has a select device electrically coupled in series with a ferroelectric capacitor.
A field effect transistor is another type of electronic component that may be used in a memory cell. These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region there-between. A conductive gate is adjacent the channel region and separated there-from by a thin gate insulator material. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structure, for example reversibly programmable charge storage regions as part of the gate construction. Transistors other than field effect transistors, for example bipolar transistors, may additionally or alternately be used in memory cells.
One type of transistor is a ferroelectric field effect transistor (FeFET) wherein at least some portion of the gate construction comprises ferroelectric material. Again, such materials are characterized by two stable polarized states. These different states in field effect transistors may be characterized by different threshold voltage (Vt) for the transistor or by different channel conductivity for a selected operating voltage. Polarization state of the ferroelectric material can be changed by application of suitable programming voltages, and which results in one of high channel conductance or low channel conductance. The high and low conductance, invoked by the ferroelectric polarization state, remains after removal of the programming gate voltage (at least for a time). The status of the channel conductance can be read by applying a small drain voltage which does not disturb the ferroelectric polarization.
Capacitors and transistors may be used in circuitry other than memory circuitry. Other types of ferroelectric devices may be utilized in integrated circuitry besides, or in addition to, ferroelectric capacitors and transistors.
Some embodiments include ferroelectric devices having ferroelectric material adjacent an electrode; and comprising a semiconductor material-containing region along a surface of the ferroelectric material nearest the electrode. The ferroelectric material may be electrically insulative. The semiconductor material-containing region has a higher concentration of semiconductor material than a remainder of the ferroelectric material. The ferroelectric devices may be, for example, ferroelectric capacitors, ferroelectric transistors, etc.
Example devices are described with reference to
Referring to
In some embodiments, the semiconductor-enriched region 18 may be considered to be a semiconductor material-containing region along a surface of the ferroelectric material 16 nearest the electrode 14.
The semiconductor-enriched region may alleviate defects associated with oxygen vacancies in the upper region of the ferroelectric material, and may thereby improve performance of the ferroelectric device 10 relative to conventional devices lacking the semiconductor-enriched region. Such alleviation of the defects may occur by introduction of semiconductor into the vacancies and/or through other mechanisms. The improved performance of ferroelectric device 10 relative to conventional devices may be evidenced by one or more of improved remnant polarization, improved endurance, improved imprint/retention, etc.
The electrode 14 comprises electrode material 20. Such electrode material may be any suitable material; and in some embodiments may comprise, consist essentially of, or consist of one or more materials selected from the group consisting of W, WN, TiN, TiCN, TiAlN, TiAlCN, Ti—W, Ru—TiN, TiOCN, RuO, RuTiON, TaN, TaAlN, TaON and TaOCN, etc., where the formulas indicate primary constituents rather than specific stoichiometries. The electrode material may include elemental metals, alloys of two or more elemental metals, conductive metal compounds, and/or any other suitable materials. Although the electrode is illustrated to comprise a single homogeneous material, in other embodiments the electrode may comprise two or more discrete separate materials.
The ferroelectric material 16 may be any suitable material. In some embodiments the ferroelectric material 16 may comprise, consist essentially of, or consist of one or more materials selected from the group consisting of transition metal oxide, zirconium, zirconium oxide, hafnium, hafnium oxide, lead zirconium titanate, tantalum oxide, and barium strontium titanate; and having dopant therein which comprises one or more of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, niobium, strontium, and a rare earth element. Although the ferroelectric material is illustrated to comprise a single homogeneous material, in other embodiments the ferroelectric material may comprise two or more discrete separate materials.
The device 10 may correspond to any of a number of ferroelectric devices.
Referring to
The electrode 22 comprises electrode material 24. Such electrode material may comprise any of the compositions described above relative to the electrode material 20 of electrode 14. The electrodes 22 and 14 may comprise the same composition as one another in some embodiments, and may comprise different compositions relative to one another in other embodiments.
In the illustrated embodiment, a semiconductor-enriched region 18 is only along an interface with one of the electrodes 14 and 22, rather than there being semiconductor-enriched regions along interfaces with each of the electrodes. However, semiconductor-enriched regions could be formed along both of the electrodes 22 and 14 if desired for a particular application.
Referring to
Source/drain regions 28 and 30 extend into the semiconductor material 26 on opposing sides of the ferroelectric material, and a channel region 32 extends under the ferroelectric material and between the source/drain regions. A separate gate dielectric is not shown between the ferroelectric material 16 and the channel region 32, but such could be provided if desired for particular applications.
The semiconductor material 26 may comprise any suitable material, and in some embodiments may comprise monocrystalline silicon. The source/drain regions 28 and 30 may be conductively-doped regions extending into the semiconductor material 26.
In some embodiments, material 26 may be considered a semiconductor substrate supporting the ferroelectric transistor 10b. The ferroelectric capacitor 10a of
Some embodiments include methods of forming ferroelectric devices. Example methods of forming ferroelectric capacitors are described with reference to
Referring to
The ferroelectric material may be an oxide-containing material; and may, for example, comprise one or more of the compositions described above with reference to
The construction 10c is converted to a construction 10d comprising the semiconductor-enriched region 18 as diagrammatically illustrated with arrow 31. Such conversion may comprise thermal treatment or other appropriate treatment to cause semiconductor material from electrode 14 to migrate into an upper portion of ferroelectric material 16 and thereby convert such upper portion to the semiconductor-enriched region 18. In embodiments in which upper electrode 14 comprises TiSiN, WSiN, HfSiN, WSi, WSiN, TaSiN or RuSi, and the semiconductor-enriched region 18 is enriched with silicon. In other embodiments, the upper electrode may comprise other semiconductor materials; such as, for example, germanium or a combination of germanium and silicon. In such other embodiments, the semiconductor-enriched region may be enriched with one or more of silicon, germanium or other suitable semiconductor material.
The conversion indicated by arrow 31 may occur with a treatment (for instance, thermal treatment) occurring after formation of electrode 14 as illustrated. Alternatively, such conversion may occur during formation of electrode 14. For instance, electrode 14 may be deposited with a mixture comprising semiconductor material, and during such deposition some of the semiconductor material may diffuse into an upper portion of ferroelectric material 16 to form the semiconductor-enriched region 18.
In some embodiments, the construction 10d of
Referring to
The semiconductor material within layer 40 is diagrammatically illustrated by stippling. Such semiconductor material may comprise any suitable semiconductor material; and in some embodiments may comprise one or both of silicon and germanium.
The layer 40 may be very thin, and in some embodiments may have a thickness within a range of from about one monolayer to less than or equal to about 100 Å. Such layer may be formed with any suitable processing, including, for example, atomic layer deposition, chemical vapor deposition, etc. In some embodiments the construction 10e is formed by depositing ferroelectric material 16 over the electrode 22, then depositing semiconductor-containing layer 40 over the ferroelectric material 16, and finally depositing the material of electrode 14 over the layer 40.
The ferroelectric material may be an oxide-containing material; and may, for example, comprise one or more of the compositions described above with reference to
The construction 10e is converted to a construction 10f comprising the semiconductor-enriched region 18 as diagrammatically illustrated with arrow 33. Such conversion may comprise thermal treatment or other appropriate treatment to cause semiconductor material from layer 40 to migrate into an upper portion of ferroelectric material 16 and thereby convert such upper portion to the semiconductor-enriched region 18. In some embodiments the layer 40 may comprise one or both of silicon and germanium, and the semiconductor-enriched region 18 may therefore be enriched with one or both of silicon and germanium.
The conversion indicated by arrow 33 may occur with a treatment (for instance, thermal treatment) occurring after formation of layer 40 and electrode 14 as illustrated. Alternatively, such conversion may occur during formation of layer 40 and/or during formation of electrode 14; or may occur after formation of layer 40 and prior to formation of electrode 14.
In some embodiments, the construction 10f of
Although the construction 10f of
Referring to
The semiconductor material within layer 42 is diagrammatically illustrated by stippling. Such semiconductor material may comprise any suitable semiconductor material; and in some embodiments may comprise one or both of silicon and germanium.
The layer 42 may be any suitable thickness, and in some embodiments may have a thickness within a range of from about 5 Å to less than or equal to about 500 Å, or less than or equal to about 30 Å. Such layer may be formed with any suitable processing, including, for example, atomic layer deposition, chemical vapor deposition, etc. In some embodiments the construction 10g is formed by depositing ferroelectric material 16 over the electrode 22, then depositing the material of electrode 14 over material 16, and finally depositing semiconductor-containing layer 42 over the electrode 14.
The ferroelectric material may be an oxide-containing material; and may, for example, comprise one or more of the compositions described above with reference to
The construction 10g is converted to a construction 10h comprising the semiconductor-enriched region 18 as diagrammatically illustrated with arrow 35. Such conversion may comprise thermal treatment or other appropriate treatment to cause semiconductor material from layer 42 to migrate through electrode 14 and into an upper portion of ferroelectric material 16. Such thereby converts such upper portion of material 16 to the semiconductor-enriched region 18. In some embodiments the layer 42 may comprise one or both of silicon and germanium, and the semiconductor-enriched region 18 may therefore be enriched with one or both of silicon and germanium.
The migration of semiconductor material from layer 42 through electrode 14 causes semiconductor material to be dispersed through electrode 14. In some embodiments, electrode 14 may consist of metal nitride (for instance titanium nitride) in construction 10g, and may comprise silicon, metal and nitrogen (for instance, may be TiSiN, WSiN, HfSiN, WSi, TaSiN, RuSi, etc., where the formulas indicates constituents and not specific stoichiometries) in construction 10h. The electrode 14 may be kept relatively thin to enable semiconductor material to diffuse entirely from layer 42 to ferroelectric material 16, and in some embodiments may have a thickness within a range of from about 5 Å to about 100 Å. The thickness of the electrode material may depend somewhat on the density of the electrode material, with less dense electrode materials being suitable for being thicker than denser electrode materials while still enabling desired diffusion of semiconductor material therethrough.
The conversion indicated by arrow 35 may occur with a treatment (for instance, thermal treatment) occurring after formation of layer 42 as illustrated. Alternatively, such conversion may occur during formation of layer 42.
In some embodiments, the construction 10h of
In some embodiments, processing similar to that of
The methods of
Some embodiments include memory arrays containing ferroelectric devices. Example memory arrays are described with reference to
Referring to
Referring to
The devices discussed above may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.
Unless specified otherwise, the various materials, substances, compositions, etc. described herein may be formed with any suitable methodologies, either now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.
Both of the terms “dielectric” and “electrically insulative” may be utilized to describe materials having insulative electrical properties. The terms are considered synonymous in this disclosure. The utilization of the term “dielectric” in some instances, and the term “electrically insulative” in other instances, may be to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.
The particular orientation of the various embodiments in the drawings is for illustrative purposes only, and the embodiments may be rotated relative to the shown orientations in some applications. The description provided herein, and the claims that follow, pertain to any structures that have the described relationships between various features, regardless of whether the structures are in the particular orientation of the drawings, or are rotated relative to such orientation.
The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections in order to simplify the drawings.
When a structure is referred to above as being “on” or “against” another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being “directly on” or “directly against” another structure, there are no intervening structures present. When a structure is referred to as being “connected” or “coupled” to another structure, it can be directly connected or coupled to the other structure, or intervening structures may be present. In contrast, when a structure is referred to as being “directly connected” or “directly coupled” to another structure, there are no intervening structures present.
Some embodiments include a ferroelectric device comprising ferroelectric material adjacent an electrode, and comprising a semiconductor material-containing region along a surface of the ferroelectric material nearest the electrode. The semiconductor material-containing region has a higher concentration of semiconductor material than a remainder of the ferroelectric material.
Some embodiments include a ferroelectric capacitor comprising oxide-containing insulative ferroelectric material between a pair of electrodes, and comprising a semiconductor material-enriched portion of the oxide-containing ferroelectric material adjacent one of the electrodes.
Some embodiments include a ferroelectric capacitor comprising a first electrode, an insulative ferroelectric material over the first electrode, and a second electrode over and directly against the ferroelectric material. The second electrode comprises metal and silicon. A silicon-enriched region of the ferroelectric material is directly against the second electrode.
Some embodiments include a ferroelectric capacitor comprising a first electrode, a ferroelectric material over the first electrode, a silicon-containing layer over and directly against the ferroelectric material, and a second electrode over and directly against the silicon-containing layer. The second electrode comprises metal.
Some embodiments include a ferroelectric capacitor comprising a first electrode, an insulative ferroelectric material over the first electrode, and a second electrode over and directly against the ferroelectric material. The second electrode comprises metal and silicon, and has a thickness within a range of from about 5 Å to about 100 Å. A silicon-containing material is over and directly against the second electrode. A silicon-enriched region of the ferroelectric material is directly against the second electrode.
Some embodiments include a method of forming a ferroelectric capacitor. An oxide-containing ferroelectric material is over a first electrode. A second electrode is formed over the oxide-containing ferroelectric material. A semiconductor material-enriched portion of the oxide-containing ferroelectric material is formed adjacent the second electrode.
In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.
