Claims
- 1. A ferroelectric memory device comprising:
memory cells, each including a ferroelectric capacitor with an insulating film of ferroelectric material and including a transistor connected to one of electrodes of the ferroelectric capacitor; a data line connected to the memory cells; and a precharge circuit for precharging said data line to a first or second precharge potential, and wherein the potential of the other electrodes of said ferroelectric capacitors of said memory cells is set to be between said first and second precharge potentials, and said precharge circuit alternatively precharges said data line with said first and second precharge potentials.
- 2. A ferroelectric memory device according to claim 1, further comprising a control circuit for controlling the potentials supplied to said precharge circuits, wherein said control circuit including a flip-flop circuit.
Parent Case Info
[0001] This application is a divisional of application Ser. No. 09/558,104, filed on Apr. 25, 2000, which, in turn, is a divisional of application Ser. No. 09/125,545, filed on Aug. 28, 1998, now U.S. Pat. No. 6,097,623, which is a section 371 of International Application PCT/JP96/00464, filed Feb. 28, 1996; and the entire disclosures of all of which are hereby incorporated by reference.
Divisions (2)
|
Number |
Date |
Country |
Parent |
09558104 |
Apr 2000 |
US |
Child |
09987590 |
Nov 2001 |
US |
Parent |
09125545 |
Aug 1998 |
US |
Child |
09558104 |
Apr 2000 |
US |