Claims
- 1. A ferroelectric memory, comprising:a memory cell including, a ferroelectric capacitor; and a select transistor whose control electrode, first electrode and second electrode are respectively connected to a word line, a bit line and said ferroelectric capacitor; and wherein the first electrode comprises a first diffused layer and the second electrode comprises a second diffused layer, and the second diffused layer has an impurity concentration lower than that of the first diffused layer.
- 2. The ferroelectric memory according to claim 1, wherein the impurity concentrations of the first and second diffused layers are respectively set to such a range that the time constant based on a reverse resistance of a junction becomes shorter than that of depolarization of said ferroelectric memory.
- 3. The ferroelectric memory according to claim 1, wherein the impurity concentration of the first diffused layer ranges from 1020/cm3 to 1021/cm3, and the impurity concentration of the second diffused layer ranges from 1018/cm3 to 1019/cm3.
Priority Claims (1)
Number |
Date |
Country |
Kind |
2000/275208 |
Sep 2000 |
JP |
|
Parent Case Info
This application is a divisional of U.S. application Ser. No. 09/741,029, filed Dec. 21, 2000.
US Referenced Citations (7)
Non-Patent Literature Citations (2)
Entry |
Ashikaga (US patent applicantion US 2002/00369150 application No: 09/741,029, filed on Dec. 21, 2000.* |
NakaMura (US patent application Publication US 2002/0036915). |