The present invention will now be described by way of example only and not in any limitative sense with reference to the accompanying drawings in which
FIG. 1 shows two field effect transistors connected in series according to a known layout;
FIG. 2 shows a FET according to the invention;
FIG. 3 shows three FETs connected in series according to a known layout;
FIG. 4 shows a further FET according to the invention;
FIG. 5 shows two dual gate FETs according to a known layout;
FIG. 6 shows a further FET according to the invention;
FIG. 7 shows a linear antenna switch according to the invention;
FIG. 8 shows a further embodiment of a linear antenna switch according to the invention;
FIG. 9 shows a further embodiment of a linear antenna switch according to the invention
Shown in FIG. 1 are two single gate field effect transistors (FETs) 1,2 connected in series and laid out in a known pattern. The first FET 1 comprises a metallic source 3 and drain 4 on a substrate (not shown). Both the source 3 and drain 4 have a plurality of fingers 5,6. The fingers 5,6 of the source 3 and drain 4 are interdigitated and separated slightly to define a meandering path 7 therebetween. Extending along the meandering path 7 is a current rectifying gate 8. The substrate is a multilayer structure housing a conducting drain source channel (not shown) channel which may be opened or closed by applying a potential to the gate 8 as is known.
The drain fingers 6 are connected to a common bar 9. Also connected to the common bar on the opposite side to the drain fingers 6 of the first FET 1 are a plurality of source fingers 10 of the second FET 2. The source fingers 10 of the second FET 2 extend away from the drain fingers 6 of the first FET 2.
The second FET 2 comprises a plurality of drain fingers 11 which are interdigitated with the second FET source fingers 10. The two sets of fingers 10,11 are slightly separated to provide a second meandering path 12. A second gate 13 extends along the meandering path 12. Such an arrangement of series connected FETs 1,2 works well in practice but uses a large amount of substrate area.
Shown in FIG. 2 is a field effect transistor 14 according to the invention. The FET 14 comprises a source 15 and a drain 16 on a substrate (not shown). Within the substrate is an electrically conducting channel. Each of the source 15 and drain 16 comprises a plurality of fingers 17,18. The fingers 17,18 are interdigitated and separated slightly to provide a meandering path 19. Extending along the meandering path 19 is an electrically conducting source/drain electrode strip 20. On each side of the source/drain electrode strip 20 is a rectifying gate strip 21. Each gate strip 21 extends parallel to the source and drain fingers 17,18 and parallel to the source/drain electrode strip 20. The gate strips 21 are adapted to control the current flow in the electrically conducting channel. A change in voltages on the gate strip 21 changes the depletion layer beneath the gate strip 21 and hence controls current flow as is known. The source/drain strip 20 is a low resistance ohmic non-rectifying strip which has minimal effect on current flow. The FET 14 according to the invention is equivalent to two single gate FETSs but takes up significantly less area.
Shown in FIG. 3 are three single gate FETs 22, 23, 24 connected in series. The structure is similar to that of FIG. 1 but now includes two common bars 25,26. Such a known structure takes up significant area.
FIG. 4 shows a further FET 27 according to the invention. As with FIG. 2 the FET 27 comprises a plurality of interdigitated source and drain fingers 28,29 defining a meandering path 30 therebetween. Extending along the meandering path 30 are two parallel spaced apart source/drain electrode strips 31. Between the source/drain electrode strips 31 is a central gate strip 32. Outside the source/drain strips 31 parallel to the source and gate fingers 28,29 are further gate strips 32. The FET 27 of this embodiment is equivalent to three single gate FETs connected in series but takes up significantly less area than the FETs 22,23,24 of FIG. 3.
Shown in FIG. 5 are two dual gate FETs 33,34 connected in series. The structure is again similar to that of FIG. 1 but each transistor 33,34 includes two gate strips 35,36,37,38 extending along its meandering path 39,40. Again, the structure takes up significant area.
FIG. 6 shows a further FET 41 according to the invention. The FET 41 is similar to that of FIG. 2 except each gate strip 21 is replaced by a pair of parallel gate strips 42,43. The FET 41 according to this embodiment is equivalent to two dual gate FETs connected in series. It takes up significantly less area than the FETs 33,34 of FIG. 5.
By changing the number of source/drain electrode contact strips and gate strips within the path between source and drain fingers one can change the properties of the transistor. As one increases the number of source/drain electrode contact strips the resulting FET becomes equivalent to an increasing number of FETs connected in series. Similarly, as one increases the number of gates one is essentially increasing the number of gates of one or more of the equivalent FETs connected in series. If one requires a FET equivalent to a number of single gate FETs connected in series one arranges the source/drain and gate strips as a repeating pattern of alternating source/drain and gate strips. Similarly, if one requires a FET equivalent to a number of dual gate FETs connected in series one arranges the strips in a repeating pattern of two gate strips and then a source/drain strip.
Shown in FIG. 7 is a linear antenna switch arm 44 according to the invention. The linear antenna switch arm comprises the field effect transistor 27 of FIG. 4. An electrically conducting signal line 45 is connected between source and drain. Connection lines 46 extend between the source drain strips 31 and the signal line 45. The connection lines 46 meet the signal line at nodes 47. Extending between the source and the first node 47 is a signal line resistor 48. Extending between the drain and the last node 47 is a further signal line resistor 49. A final signal line resistor 50 extends between the nodes 47. The equivalent circuit is shown alongside.
Shown in FIG. 8 is a further embodiment of a linear antenna switch arm 51 according to the invention. Again, the equivalent circuit is shown alongside. This embodiment lacks a signal line resistor between nodes 47. Each of the connection lines 46 includes a resistor 52,53.
Shown in FIG. 9 is a further embodiment of a linear antenna switch arm 54 according to the invention. Again the equivalent circuit is shown alongside. This embodiment is similar to that of FIG. 8 except it lacks a signal line resistor 48 between source and node 47. In an alternative embodiment (not shown) it is the signal line resistor between node and drain which is omitted.
In the embodiments of the linear antenna switch arm according to the invention disclosed above the FETs employed are equivalent to single gate FETs connected in series. Other FETs according to the invention can be used as part of the linear antenna switch arm having different arrangements of gate and source/drain strips.
Patent Application
20080042919
