Patent Application
20060046402
The present invention relates generally to integrated circuit devices, and in particular the present invention relates to flash cell structures and methods of formation.
Memory devices are typically provided as internal storage areas in a computer. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address.
One type of memory is a non-volatile memory known as Flash memory. A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that can be erased and reprogrammed in blocks. Many modern personal computers (PCs) have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in wireless electronic devices because it enables the manufacturer to support new communication protocols as they become standardized and to provide the ability to remotely upgrade the device for enhanced features.
A typical flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
Flash memory typically utilizes one of two basic architectures known as NOR flash and NAND flash. The designation is derived from the logic used to read the devices. In NOR flash architecture, a column of memory cells are coupled in parallel with each memory cell coupled to a bit line. In NAND flash architecture, a column of memory cells are coupled in series with only the first memory cell of the column coupled to a bit line.
Memory device fabricators are continuously seeking to reduce the size of the devices. Smaller devices facilitate higher productivity and reduced power consumption. However, as device sizes become smaller, resistance of the various conductors becomes an ever-increasing problem. High resistance can lead to slower performance. One solution is to utilize materials having higher conductivity.
Flash devices need high capacitive coupling between the control gate and the floating gate because of performance requirements. A traditional flash structure is shown in several stages of fabrication in
Recently, an approach eliminating deep ultra-violet (DUV) patterning by performing an oxide etch back was proposed. This approach reduces costs, but capacitive coupling degrades because the width of the floating gate is reduced. Proposed remedies such as increasing the poly height are limited due to the increase in gate resistance with such a proposal, as well as manufacturing difficulties and scaling issues.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved fabrication techniques, and improved coupling ratios in flash memory structures.
The above-mentioned problems with flash memory structures and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a method of fabricating an array of floating gate memory cells includes forming a tunnel oxide layer over a number of columns surrounded by shallow trenches, forming a thick polysilicon floating gate over the tunnel oxide layer, forming a set of spacers at the edge of each floating gate, forming a dielectric layer over the trenches, the spacers, and the floating gates, and forming a control gate over the dielectric layer.
In another embodiment, a method of fabricating an array of floating gate memory cells includes forming a tunnel oxide layer over a number of columns surrounded by shallow trenches, forming a thick polysilicon floating gate over the tunnel oxide layer, patterning a second polysilicon layer to control height and width of the floating gate, forming a dielectric layer over the trenches and the floating gates, and forming a control gate over the dielectric layer.
In still another embodiment, a method of controlling a coupling ratio in a flash memory cell includes controlling a height and a width of a floating gate of the flash memory cell.
In yet another embodiment, a floating gate memory cell array includes a number of shallow trenches filled with a dielectric material, a number of columns surrounded by the shallow trenches, a tunnel oxide layer at the top of each column, a thick polysilicon floating gate over each tunnel oxide layer, a set of spacers at an edge of each floating gate, the spacers over the dielectric material of the trenches, a dielectric layer over the trenches, the spacers, and the floating gates, and a control gate over the dielectric layer.
In still another embodiment, an array of floating-gate field-effect transistors includes two or more columns of the floating-gate field-effect transistors. Each field-effect transistor of a column includes a tunnel oxide, a thick polysilicon floating gate formed over the tunnel oxide, spacers at the edge of the floating gate, a dielectric layer formed over the spacers and the floating gate, and a control gate formed over the dielectric layer.
Other embodiments are described and claimed.
In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention.
The terms wafer and substrate used previously and in the following description include any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and their equivalents.
The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
A nitride layer 220 is formed over the first polysilicon layer 215. Trench 225 is formed by photolithographic etching to form shallow trenches. Shallow trench isolation (STI) methods are known in the art and will not be described further herein. Following STI, an STI fill is performed, as is shown in
In the present embodiment, the floating gate deposition required by the prior art process is not performed, since the polysilicon that will form the floating gate is already present in the structure. Instead, a second polysilicon spacer layer 240 is deposited as is shown in
From the structure of
Oxide-nitride-oxide layer 255 may also be any dielectric layer. Other dielectric materials may be substituted for the ONO, such as tantalum oxide, barium strontium titanate, silicon nitride and other materials providing dielectric properties.
In traditional prior art fabrication, a thinner first polysilicon layer is used, typically on the order of 200-400 Angstroms. The process of formation is similar until after the nitride strip process. At this point in typical prior art fabrication techniques, floating gate polysilicon deposition followed by a photolithographic etch is performed, using a floating gate mask. In the present embodiments, the separate deposition of a floating gate polysilicon layer is eliminated, since the thick polysilicon deposition discussed above with respect to
In the process and structure shown in
Advantages of the embodiments of
Each memory cell is located at an intersection of a word line and a local bit line. The memory array 402 is arranged in rows and columns, with the rows arranged in blocks. A memory block is some discrete portion of the memory array 402. Individual word lines generally extend to only one memory block while bit lines may extend to multiple memory blocks. The memory cells generally can be erased in blocks. Data, however, may be stored in the memory array 402 separate from the block structure.
The memory array 402 is arranged in a plurality of addressable banks. In one embodiment, the memory contains four memory banks 404, 406, 408 and 410. Each memory bank contains addressable sectors of memory cells. The data stored in the memory can be accessed using externally provided location addresses received by address register 412 from processor 401 on address lines 413. The addresses are decoded using row address multiplexer circuitry 414. The addresses are also decoded using bank control logic 416 and row address latch and decode circuitry 418.
To access an appropriate column of the memory, column address counter and latch circuitry 420 couples the received addresses to column decode circuitry 422. Circuit 424 provides input/output gating, data mask logic, read data latch circuitry and write driver circuitry. Data is input through data input registers 426 and output through data output registers 428. This bi-directional data flow occurs over data (DQ) lines 443.
Command execution logic 430 is provided to control the basic operations of the memory device including memory read operations. A state machine 432 is also provided to control specific operations performed on the memory arrays and cells. A high voltage switch and pump circuit 445 is provided to supply higher voltages during erase and write operations. A status register 434 and an identification register 436 can also be provided to output data.
The memory device 400 can be coupled to an external memory controller, or processor 401, to receive access commands such as read, write and erase command. Other memory commands can be provided, but are not necessary to understand the present invention and are therefore not outlined herein. The memory device 400 includes power supply inputs Vss and Vcc to receive lower and upper voltage supply potentials.
As stated above, the flash memory device 401 has been simplified to facilitate a basic understanding of the features of the memory device. A more detailed understanding of flash memories is known to those skilled in the art. As is well known, such memory devices 401 may be fabricated as integrated circuits on a semiconductor substrate. The memory cells described above are used in various embodiments in the basic memory array or system structure described in
Memory cell structures and methods of fabrication have been described that include controlling the coupling ratio between the floating gate and the control gate, cost reduction in processing, and elimination of some fabrication processes. The embodiments of the present invention remove processing steps and subject the structure to less processing, reducing costs, but also improving control of capacitive coupling in the memory structure, and increasing active area of the resulting structures.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement, which is calculated to achieve the same purpose, may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.
