The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.
Non-volatile memory cells are well known in the art. One prior art non-volatile split gate memory cell 10, which contains five terminals, is shown in
One exemplary operation for erase and program of prior art non-volatile memory cell 10 is as follows. Memory cell 10 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on erase gate 28 with other terminals equal to zero volt. Electrons tunnel from floating gate 24 into erase gate 28 causing floating gate 24 to be positively charged, turning on the cell 10 in a read condition. The resulting cell erased state is known as ‘1’ state.
Memory cell 10 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on coupling gate 26, a high voltage on source line 14, a medium voltage on erase gate 28, and a programming current on bit line 20. A portion of electrons flowing across the gap between word line 22 and floating gate 24 acquire enough energy to inject into floating gate 24 causing the floating gate 24 to be negatively charged, turning off the cell 10 in a read condition. The resulting cell programmed state is known as ‘0’ state.
Memory cell 10 is read in a Current Sensing Mode as following: A bias voltage is applied on bit line 20, a bias voltage is applied on word line 22, a bias voltage is applied on coupling gate 26, a bias or zero voltage is applied on erase gate 28, and a ground is applied on source line 14. There exists a cell current flowing from bit line 20 to source line 14 for an erased state and there is insignificant or zero cell current flow from the bit line 20 to the source line 14 for a programmed state. Alternatively, memory cell 10 can be read in a Reverse Current Sensing Mode, in which bit line 20 is grounded and a bias voltage is applied on source line 24. In this mode the current reverses the direction from source line 14 to bitline 20.
Memory cell 10 alternatively can be read in a Voltage Sensing Mode as following: A bias current (to ground) is applied on bit line 20, a bias voltage is applied on word line 22, a bias voltage is applied on coupling gate 26, a bias voltage is applied on erase gate 28, and a bias voltage is applied on source line 14. There exists a cell output voltage (significantly >0V) on bit line 20 for an erased state and there is insignificant or close to zero output voltage on bit line 20 for a programmed state. Alternatively, memory cell 10 can be read in a Reverse Voltage Sensing Mode, in which bit line 20 is biased at a bias voltage and a bias current (to ground) is applied on source line 14. In this mode, memory cell 10 output voltage is on the source line 14 instead of on the bit line 20.
In the prior art, various combinations of positive or zero voltages were applied to word line 22, coupling gate 26, and floating gate 24 to perform read, program, and erase operations
In response to the read, erase or program command, the logic circuit 270 (in
For the selected and unselected memory cell 10, the voltage and current applied are as follows. As used hereinafter, the following abbreviations are used: source line or first region 14 (SL), bit line 20 (BL), word line 22 (WL), and coupling gate 26 (CG).
In a recent application by the applicant—U.S. patent application Ser. No. 14/602,262, filed on Jan. 21, 2015, which is incorporated by reference—the applicant disclosed an invention whereby negative voltages could be applied to word line 22 and/or coupling gate 26 during read, program, and/or erase operations. In this embodiment, the voltage and current applied to the selected and unselected memory cell 10, are as follows.
In another embodiment of U.S. patent application Ser. No. 14/602,262, negative voltages can be applied to word line 22 when memory cell 10 is unselected during read, erase, and program operations, and negative voltages can be applied to coupling gate 26 during an erase operation, such that the following voltages are applied:
The CGINH signal listed above is an inhibit signal that is applied to the coupling gate 26 of an unselected cell that shares an erase gate 28 with a selected cell.
With flash memory systems becoming ubiquitous in all manner of computing and electronic devices, it is increasingly important to create designs that reduce the amount of die space required per memory cell and to reduce the overall complexity of decoders use in flash memory systems. What is needed is flash memory cell design that utilizes fewer terminals than in the prior art and simplified circuitry for operating flash memory cells that follow that design.
The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.
The erase operation (erasing through erase gate) and read operation are similar to that of the
Table No. 4 depicts typical voltage ranges that can be applied to the four terminals for performing read, erase, and program operations:
Die 500 further comprises the following functional structures and sub-systems: macro interface pins ITFC pin 548 for interconnecting to other macros on a SOC (system on chip); low voltage generation (including a low voltage charge pump circuit) circuits 547 and high voltage generation (including a high voltage charge pump circuit) circuit 546 used to provide increased voltages for program and erase operations for memory arrays 501, 511, 521, and 531; analog circuit 544 used by analog circuitry on die 500; digital logic circuit 545 used by digital circuitry on die 500.
Row decoder 600 further comprises inverter 602, decoder circuit 610 to generate word line WL0, decoder circuit 620 to generate WL7, as well as additional decoder circuits (not shown) to generate word lines WL1, WL2, WL3, WL4, WL5, and WL6.
Decoder circuit 610 comprises PMOS transistors 611, 612, and 614 and NMOS transistors 613 and 615, configured as shown. Decoder circuit 610 receives the output of NAND gate 601, the output of inverter 602, and pre-decoded address signal XPZB0. When this particular sector is selected and XPZB0 is “low,” then WL0 will be asserted. When XPZB0 is “high,” then WL0 will not be asserted.
Similarly, decoder circuit 620 comprises PMOS transistors 621, 622, and 624 and NMOS transistors 623 and 625, configured as shown. Decoder circuit 620 receives the output of NAND gate 601, the output of inverter 602, and pre-decoded address signal XPZ70. When this particular sector is selected and XPZB7 is “low,” then WL7 will be asserted. When XPZB7 is “high,” then WL7 will not be asserted.
It is to understood that the decoder circuits (now shown) for WL1, WL2, and WL3, WL4, WL5, and WL6 will follow the same design as decoder circuits 610 and 620 except that they will receive the inputs XPZB1, XPZB2, XPZB3, XPZB4, XPZB5, and XPZB6, respectively, instead of XPZB0 or XPZB7.
In the situation where this sector is selected and it is desired for WL0 to be asserted, the output of NAND gate 601 will be “low,” and the output of inverter will be “high.” PMOS transistor 611 will be turned on, and the node between PMOS transistor 612 and NMOS transistor 613 will receive the value of XPZB0, which will be “low” when word line WL0 is to be asserted. This will turn on PMOS transistor 614, which will pull WL0 “high” to ZVDD which indicates an asserted state. In this instance, XPZB7 is “high,” signifying that WL7 is to be not asserted, which will pull the node between PMOS transistor 622 and NMOS transistor 623 to the value of XPZB7 (which is “high”), which will turn on NMOS transistor 624 and cause WL to be “low,” which indicates a non-asserted state. In this manner, one of the word lines WL0 . . . WL7 can be selected when this sector is selected.
High voltage level shift enable circuit 710 comprises high voltage level shift circuit 711 and low voltage latch 712. Low voltage latch 712 receives word line (WL), enable (EN), and reset (RST) as input signals and outputs sector enable signal (SECEN) and sector enable signal bar (SECEN_N). Sector enable signal (SECEN) is provided as an input to high voltage level shift circuit 711, which outputs sector enable signal high voltage (SECEN_HV0 . . . SECEN_HVN for N sectors) and sector enable signal high voltage bar (SECEN_HV0_N . . . SECEN_HVN _N for N sectors).
Erase gate decoder 720 comprises erase gate decoder 721 for row 0 in the sector, and similar erase gate decoders (not shown) for rows 1, . . . , N in the sector. Here, erase gate decoder 721 receives the sector enable signal high voltage (SECEN_HV0) from high voltage level shift circuit 711, its complement (SECEN_HV0_N), a voltage erase gate supply (VEGSUP), a low voltage erase gate supply (VEGSUP_LOW), sector enable signal (SECEN), and its complement (SECEN_N). Thus, the output EG0 of erase gate decoder 721 can be at one of three different voltage levels: SECEN_HV0 (high voltage), VEGSUP (normal voltage), or VEGSUP_LOW (low voltage).
Similarly, source line decoder 730 comprises source line decoder 721 for row 0 in the sector, and similar source line decoders (not shown) for rows 1, . . . , N in the sector. Here, source line decoder 731 receives sector enable signal high voltage (SECEN_HV0) from high voltage level shift circuit 711, its complement (SECEN_HV0_N), a voltage source line supply (VSLSUP), a low voltage source line supply (VSLSUP LOW), sector enable signal (SECEN), and its complement (SECEN_N). Thus, the output SL0 of source line decoder 730 can be at one of three different voltage levels: SECEN_HV0 (high voltage), VSLSUP (normal voltage), or VSLSUP_LOW (low voltage).
When selected memory cell 1610 is in program mode, bitline 1526 is coupled to an inhibit voltage such as VDD. This will place dummy memory cell 1510 in a program inhibit mode which will maintain dummy memory cell 1520 in am erased state. A plurality of the dummy cells, such as dummy memory cell 1510, can be connected to memory cell 1610 through their source lines to strengthen the pull down of the source line 1620 to ground.
This application is a divisional of U.S. patent application Ser. No. 16/879,663, filed on May 20, 2020, titled, “Flash Memory Cell and Associated High Voltage Row Decoder,” and issued as U.S. Pat. No. 11,011,240 on May 18, 2021, which is a divisional of U.S. patent application Ser. No. 15/924,100, filed on Mar. 16, 2018, titled “Flash Memory Cell and Associated Decoders,” and issued as U.S. Pat. No. 10,741,265 on Aug. 11, 2020, which is a divisional of U.S. patent application Ser. No. 15/158,460, filed on May 18, 2016, titled, “Flash Memory Cell And Associated Decoders,” and issued as U.S. Pat. No. 9,953,719 on Apr. 24, 2018, all of which are incorporated by reference herein.
Number | Name | Date | Kind |
---|---|---|---|
4511881 | Adam | Apr 1985 | A |
6044020 | Chung et al. | Mar 2000 | A |
6282145 | Tran | Aug 2001 | B1 |
9361995 | Tran | Jun 2016 | B1 |
20020126550 | Sugio | Sep 2002 | A1 |
20040212008 | Hasegawa | Oct 2004 | A1 |
20060083064 | Toshiaki | Apr 2006 | A1 |
20070025171 | Kuroda | Feb 2007 | A1 |
20070230253 | Kim | Oct 2007 | A1 |
20080315918 | Luo | Dec 2008 | A1 |
20090180317 | Kang | Jul 2009 | A1 |
20100054043 | Liu | Mar 2010 | A1 |
20100128522 | Choi et al. | May 2010 | A1 |
20100188900 | Tran | Jul 2010 | A1 |
20100301927 | Nagai | Dec 2010 | A1 |
20110122693 | Tran et al. | May 2011 | A1 |
20120268187 | Kimoto | Oct 2012 | A1 |
20140192596 | Rhie | Jul 2014 | A1 |
20140269062 | Do et al. | Sep 2014 | A1 |
20150063027 | Hashimoto | Mar 2015 | A1 |
20150194961 | Luthra | Jul 2015 | A1 |
Number | Date | Country |
---|---|---|
H02 276095 | Nov 1990 | JP |
H07 111840 | Nov 1995 | JP |
H11 220111 | Aug 1999 | JP |
2013 200932 | Oct 2013 | JP |
2014 029745 | Feb 2014 | JP |
2014 183233 | Sep 2014 | JP |
2015 049916 | Mar 2015 | JP |
2015 536011 | Dec 2015 | JP |
201618285 | May 2016 | TW |
2016 053607 | Jul 2016 | WO |
Number | Date | Country | |
---|---|---|---|
20210241839 A1 | Aug 2021 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 16879663 | May 2020 | US |
Child | 17239397 | US | |
Parent | 15924100 | Mar 2018 | US |
Child | 16879663 | US | |
Parent | 15158460 | May 2016 | US |
Child | 15924100 | US |