Flash memory device and related erase operation

Abstract

An erase operation for a flash memory device includes identifying a sector group including a plurality of sectors based on an address, simultaneously pre-programming the sectors in the sector group, simultaneously erasing the sectors the sector group, and simultaneously post-programming the sectors in the sector group.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a conventional flash memory cell.

FIG. 2 is a graph illustrating the distribution of threshold voltages of an ON cell and an OFF cell in the conventional flash memory cell of FIG. 1.

FIG. 3 illustrates an erase operation for a conventional NOR flash memory device and corresponding threshold voltages derived during the erase operation.

FIG. 4 is a general block diagram of a NOR flash memory device according to one embodiment of the invention.

FIG. 5 is an exemplary configuration diagram of the memory cell array shown in FIG. 4.

FIG. 6 is a flowchart illustrating an erase operation for a NOR flash memory device according to an embodiment of the invention.

FIG. 7 is a flowchart illustrating an exemplary pre-programming operation for the multi-sector shown in FIG. 6.

FIG. 8 is a flowchart illustrating an exemplary main erasing operation for the multi-sector shown in FIG. 6.

FIG. 9 is a flowchart illustrating an exemplary post-programming operation for the multi-sector shown in FIG. 6.

Claims

1. An erase operation for a flash memory device, comprising: (a) identifying a sector group including a plurality of sectors in relation to an address;(b) simultaneously pre-programming the sectors in the sector group;(c) simultaneously erasing the sectors the sector group; and(d) simultaneously post-programming the sectors in the sector group.

2. The erase operation of claim 1, further comprising: following (a), repeating (b), (c), and (d) until all sectors corresponding to the address are erased.

3. The erase operation of claim 1, wherein the sectors in the sector group have the same row address.

4. The erase operation of claim 1, wherein the sectors in the sector group are arranged in different banks.

5. The erase operation of claim 1, wherein the number of sectors in the sector group is determined by the sector that may be simultaneously programmed in the flash memory device or the number of sector that may be simultaneously erased in the flash memory device.

6. The erase operation of claim 1, wherein the (b) comprises: (b1) simultaneously pre-programming the sectors in the sector group;(b2) marking sectors to be pre-programmed among the sectors in the sector group in response to the address; and(b3) simultaneously pre-programming the marked sectors.

7. The erase operation of claim 6, further comprising: omitting (b) when no sector is marked.

8. The erase operation of claim 1, wherein the (c) comprises: (c1) marking sectors to be erased among the sectors in the sector group; and(c2) simultaneously erasing the marked sectors.

9. The erase operation of claim 8, further comprising: omitting (c) when sector is marked.

10. The erase operation of claim 1, wherein the (d) comprises: (d1) marking sectors to be post-programmed among the sectors in the sector group; and(d2) simultaneously post-programming the marked sectors.

11. The erase operation of claim 10, further comprising: omitting (d) when no sector is marked.

12. A flash memory device comprising: a memory cell array including a plurality of banks each having a plurality of sectors;a controller adapted to identify a sector group including a plurality of the sectors in response to a received address; anda plurality of write drivers adapted to simultaneously erase the sectors in the sector group under control of the controller.

13. The flash memory device of claim 12, wherein the write drivers simultaneously performs each one of pre-programming, main erasing, and post-programming operations for corresponding sectors in the sector group.

14. The flash memory device of claim 13, wherein the pre-programming, main erasing, and post-programming operations are repeatedly performed until all sectors corresponding to the address are erased.

15. The flash memory device of claim 13, further comprising: a plurality of sense amplifiers adapted to sense results of the pre-programming, main-erasing, and post-programming operations for the corresponding sectors in the sector group under control of the controller.

16. The flash memory device of claim 12, wherein the sectors in the sector group are arranged in different ones of the plurality of banks.

17. The flash memory device of claim 12, wherein the sectors in the sector group have the same row address.

18. The flash memory device of claim 12, wherein the number of sectors in the sector group is determined in relation to the maximum number of sector that may be simultaneously programmed within the flash memory device or the maximum number of sectors that may be simultaneously erased in the flash memory device.

19. The flash memory device of claim 13, wherein the controller marks sectors to be pre-programmed among the plurality of the sectors in response to the address.

20. The flash memory device of claim 19, wherein the marked sectors are simultaneously pre-programmed.

21. The flash memory device of claim 19, wherein the pre-programming operation for the sectors is omitted when there is no marked sector among the sectors in the sector group.

22. The flash memory device of claim 13, wherein the controller marks sectors to be main-erased among the plurality of the sectors in response to the address.

23. The flash memory device of claim 22, where among the sectors in the sector group, the marked sectors are simultaneously erased.

24. The flash memory device of claim 22, wherein the main erasing operation for the sectors is omitted when there is no marked sector among the sectors in the sector group.

25. The flash memory device as recited 13, wherein the controller marks sectors to be post-programmed among the plurality of the sectors in response to the address.

26. The flash memory device of claim 25, wherein among the sectors in the sector group, the marked sectors are simultaneously post-programmed.

27. The flash memory device of claim 25, wherein the post-programming operation for the sectors is omitted when there is no marked sector among the sectors in the sector group.