Patent Grant
9564238
The present application claims priority under 35 U.S.C. Section 119 to Patent Application 201510647190.0, titled “Flash Memory System Using Memory Cell As Source Line Pull Down Circuit” and filed in the People's Republic of China on Sep. 11, 2015, which is incorporated by reference herein.
The present invention relates to a flash memory device that uses dummy memory cells as source line pull down circuits.
Non-volatile memory cells are well known in the art. A first type of prior art non-volatile memory cell 110 is shown in
One exemplary operation for erase and program of prior art non-volatile memory cell 110 is as follows. The cell 110 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the word line 122 and zero volts to the bit line and source line. Electrons tunnel from the floating gate 124 into the word line 122 causing the floating gate 124 to be positively charged, turning on the cell 110 in a read condition. The resulting cell erased state is known as ‘1’ state. The cell 110 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the source line 114, a small voltage on the word line 122, and a programming current on the bit line 120. A portion of electrons flowing across the gap between the word line 122 and the floating gate 124 acquire enough energy to inject into the floating gate 124 causing the floating gate 124 to be negatively charged, turning off the cell 110 in read condition. The resulting cell programmed state is known as ‘0’ state.
Exemplary voltages that can be used for the read, program, erase, and standby operations in memory cell 110 is shown below in Table 1:
A second type of prior art non-volatile memory cell 210 is shown in
One exemplary operation for erase and program of prior art non-volatile memory cell 210 is as follows. The cell 210 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the word line 222 with other terminals equal to zero volt. Electrons tunnel from the floating gate 224 into the word line 222 to be positively charged, turning on the cell 210 in a read condition. The resulting cell erased state is known as ‘1’ state. The cell 210 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate 226, a high voltage on the source line 214, and a programming current on the bit line 220. A portion of electrons flowing across the gap between the word line 222 and the floating gate 224 acquire enough energy to inject into the floating gate 224 causing the floating gate 224 to be negatively charged, turning off the cell 210 in read condition. The resulting cell programmed state is known as ‘0’ state.
Exemplary voltages that can be used for the read, program, erase, and standby operations in memory cell 210 is shown below in Table 2:
Another set of exemplary voltages (when a negative voltage is available for read and program operations) that can be used for the read, program, and erase operations in memory cell 210 is shown below in Table 3:
Another set of exemplary voltages (when a negative voltage is available for read, program, and erase operations) that can be used for the read, program, and erase operations in memory cell 210 is shown below in Table 4:
A third type of non-volatile memory cell 310 is shown in
One exemplary operation for erase and program of prior art non-volatile memory cell 310 is as follows. The cell 310 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate 328 with other terminals equal to zero volt. Electrons tunnel from the floating gate 324 into the erase gate 328 causing the floating gate 324 to be positively charged, turning on the cell 310 in a read condition. The resulting cell erased state is known as ‘1’ state. The cell 310 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate 326, a high voltage on the source line 314, a medium voltage on the erase gate 328, and a programming current on the bit line 320. A portion of electrons flowing across the gap between the word line 322 and the floating gate 324 acquire enough energy to inject into the floating gate 324 causing the floating gate 324 to be negatively charged, turning off the cell 310 in read condition. The resulting cell programmed state is known as ‘0’ state.
Exemplary voltages that can be used for the read, program, and erase operations in memory cell 310 is shown below in Table 5:
For programming operation, the EG voltage can be applied much higher, e.g. 8V, than the SL voltage, e.g., 5V, to enhance the programming operation. In this case, the unselected CG program voltage is applied at a higher voltage (CG inhibit voltage), e.g. 6V, to reduce unwanted erase effect of the adjacent memory cells sharing the same EG gate of the selected memory cells.
Another set of exemplary voltages (when a negative voltage is available for read and program operations) that can be used for the read, program, and erase operations in memory cell 310 is shown below in Table 6:
Another set of exemplary voltages (when a negative voltage is available for read, program, and erase operations) that can be used for the read, program, and erase operations in memory cell 310 is shown below in Table 7:
For programming operation, the EG voltage is applied much higher, e.g. 8-9V, than the SL voltage, e.g., 5V, to enhance the programming operation. In this case, the unselected CG program voltage is applied at a higher voltage (CG inhibit voltage), e.g. 5V, to reduce unwanted erase effects of the adjacent memory cells sharing the same EG gate of the selected memory cells.
Memory cells of the types shown in
For each of the prior art memory cells of
What is needed is a new technique for pulling source lines to ground in a flash memory system that can use the same operating voltage range as the memory cells themselves and that are more robust to over stress and break down.
In the embodiments described below, flash memory devices utilize dummy memory cells as source line pull down circuits.
An embodiment is shown in
When memory cell 410 is in read mode or erase mode, source line 514 is coupled to ground through the memory cell 510 to dummy bitline 520 which is coupled to ground. The dummy memory cells 150 are required to be erased before read operation. This will pull source line 414 and source line 514 to ground.
When the memory cell 410 is in program mode, the bitline line 520 is coupled to an inhibit voltage such as VDD. This will place the dummy memory cell 510 in a program inhibit mode which maintain the dummy memory cells in erased state. There is a plurality of the dummy cells 520 to strengthen the pull down of the source line 414 to ground.
Another embodiment is shown in
Thus, the source lines for an entire sector or sectors of memory cells can be coupled together to a source line of dummy memory cell circuit comprising dummy memory cells from the same rows of cells that are part of the sector or sectors.
When memory cell 620 are in read mode or erase mode, dummy memory cell circuit 620 will be coupled to ground through the dummy bitlines. The dummy memory cells are required to be erased before read operation. This will pull source lines 630 and 640 to ground.
When memory cell 620 are in program mode, the dummy bitlines of memory cell circuit 620 will be coupled to an inhibit voltage such as VDD. This will place dummy memory cells in a program inhibit mode which maintain the dummy memory cells in erased state.
Optionally, word line 650 (also labeled WL_rdcellpdwn, which is separate from wordlines of the memory cell 620) and control gate 660 (also labeled CG_rdcellpdwn, which is separate from control gates for the memory cell 620) are biased at a different voltage than that of the memory cell 620 such as VDD or higher during read or standby modes to minimize the current drop across the dummy memory cells.
The embodiments of
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015 1 0647190 | Sep 2015 | CN | national |
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|---|---|---|---|
| 20060139997 | Park | Jun 2006 | A1 |
| 20090180317 | Kang | Jul 2009 | A1 |
| 20110085385 | Park | Apr 2011 | A1 |
| 20140063985 | Joo | Mar 2014 | A1 |
