Patent Application
20080055288
The present invention relates to a flat display apparatus and a driving method for the same, and more particularly to a flat display apparatus, such as a plasma display panel (PDP), that is self-emissive, can achieve a large-screen display, and consumes relatively large power, and a driving method for the same.
In recent years, flat panel displays have been supplanting traditional CRT-based displays and finding wide practical application as displays ranging from small-area to large-area displays. Liquid crystal displays (LCDs) and organic electroluminescent (EL) displays, as small-area displays, and plasma displays, as large-area displays, have been commercially implemented by exploiting their respective features. To promote further prevalence of flat panel displays in future, it is desired to further reduce the costs of the displays and improve their display characteristics while, at the same time, achieving significant improvements in functions and performance. Furthermore, today there is an increasing need to reduce environmental loads, and it is strongly demanded to reduce the power consumption of such displays in order to promote widespread use in ordinary homes.
As is known in the art, a surface-discharge type plasma display apparatus, for example, has been commercially implemented as a flat-panel image display apparatus; in this type of display apparatus, all pixels on the screen are driven simultaneously to emit light in accordance with the display image data. The surface-discharge type plasma display apparatus has a structure such that a pair of electrodes are formed on the inside surface of a front glass substrate and a rare gas is filled therein. When a voltage is applied between the electrodes, a surface discharge occurs at the surface of a protective layer and dielectric layer formed on the electrode surface, resulting in the emission of ultraviolet light. The inside surface of a rear glass substrate is coated with phosphors of three primary colors, red (R), green (G), and blue (B), which when excited by the ultraviolet light, produce visible light to achieve a color display.
As shown in
The control circuit 2 comprises a display data control section 21 for controlling the address driver 3 and a panel driving control section for controlling the scan driver 4, the X-common driver 5, and the Y-common driver 6; the control circuit 2 receives various synchronization signals (dot clock CLK, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync) as well as display image data DATA representing the luminance levels of three primary colors, R, G, and B, from an external apparatus such as a TV tuner or a computer, and supplies suitable control signals to the address driver 3, the scan driver 4, the X-common driver 5, and the Y-common driver 6 in order to produce a desired image display. Here, the display data control section 21 includes a frame memory 21 for temporarily storing the input display image data, while the panel driving control section 22 includes a scan driver controller 221 for controlling the scan driver 4 and a common driver controller 222 for controlling the X-common driver 5 and the Y common driver.
The address driver 3 is constructed as an address driver IC for generating an address pulse (address discharge voltage) corresponding to the display image data DATA for individual address electrodes A1 to Am(16); the X-common driver 5 is constructed as an X-common driver circuit for generating a sustain pulse (sustain discharge voltage) for X electrodes X1 to Xn(12); the Y-common driver 6 is constructed as a Y-common driver circuit for generating a sustain pulse for Y electrodes Y1 to Yn(13) via the scan driver 4; and the scan driver 4 is constructed as a scan driver IC for driving the Y electrodes Y1 to Yn independently of each other for scanning.
Work has been proceeding in recent years to develop a scan driver IC that incorporates a sustain pulse generating function, thereby eliminating the need for the Y-common driver 6 as the sustain pulse generating circuit and achieving a reduction in size. Driving waveforms generated by the address driver 3, the scan driver 4, the X-common driver 5, and the Y-common driver 6, and having prescribed voltage levels to be applied to the respective electrodes, will be described later with reference to
In
Further, the gap between the front glass substrate 11, on which the X electrode 12 and Y electrode 13 are formed, and the rear glass substrate 16, on which the address electrodes 16 are formed so as to intersect at right angles with the X electrode 12 and Y electrode 13, is filled with a discharge gas such as a neon/xenon mixture gas, and a discharge space at each intersection between the address electrodes and the X and Y electrodes forms one discharge cell.
In the address electrode structure of the PDP 1, a relatively small capacitor (parasitic capacitor) Cg is formed between opposing electrodes (between address electrode 16 and X electrode 12 or between address electrode 16 and Y electrode 13) because of the interposition of the glow discharge gas space, while on the other hand, a relatively large capacitor (parasitic capacitor) Ca is formed between adjacent electrodes (for example, between adjacent address electrodes) because of the presence of an insulating layer between them. The power consumption of the plasma display apparatus increases with increasing frequencies of operation that causes the capacitor Ca between the adjacent electrodes to charge and discharge for each switching of scanning operation, and the power consumption becomes the largest when such charge and discharge occurs in every scanning operation.
A specific example of a display pattern for which the power consumption becomes the largest is a display pattern that causes the ON and OFF states to be reversed between adjacent address electrodes for each scanning operation; in the case of progressive scanning operation, a staggered dot pattern is a typical example. The power consumption when displaying such a pattern is about two to three times as large as that when displaying a standard average pattern.
As shown in
As shown in
In the address period, a scan pulse of −Vy level is applied to the scan electrodes, i.e., the Y electrodes (Y1 to Yn: 13), in sequence by switching from one electrode to the next and, in synchronism with the application of the scan pulse to each Y electrode, an address pulse of Va level is applied to each address electrode (A1 to Am: 13), thereby selecting pixels on the Y electrode.
In the sustain period TS, sustain pulses of common levels Vsy and Vsx (sustain discharge voltage) are applied to all the scan electrodes (Y1 to Yn: 13) and common X electrodes (X1 to Xn: 12) in alternating fashion, thus causing the selected pixels to emit light, and a display with desired brightness is produced by continuous application of such pulses. A desired grayscale image is displayed by controlling the number of emissions by appropriately combining the basic operations of these series of driving waveforms.
As earlier described, the power consumption of the address electrode driver in the plasma display apparatus increases with increasing frequencies of operation that causes the capacitor Ca between the adjacent electrodes to charge and discharge for each switching of scanning operation; in the prior art, to reduce the power consumption of the address driver, there is proposed a plasma display apparatus in which a prescribed time lag is provided between the rising of the address pulse signal for a first address electrode and the falling of the address pulse signal for a second address electrode adjacent to the first address electrode (for example, refer to patent document 1).
Further, in a prior art driving method for a plasma display panel (PDP) of the type in which electrons are always stored on the scan electrode side, there is proposed a plasma display apparatus wherein provisions are made to increase bias voltage in order to compensate for the display characteristics of the PDP by preventing the electrons stored on the scan electrode side from tending to be emitted as the temperature of the PDP rises (for example, refer to patent document 2).
In the prior art, there is also proposed a PDP display apparatus comprising a PDP driving circuit for supplying driving power to the PDP and a controller for controlling the driving power wherein the PDP driving circuit outputs the driving power based on a power correction value generated by a voltage adjusting circuit included in the controller (for example, refer to patent document 3). The prior art further proposes a plasma display apparatus wherein when the panel temperature rises or when the panel is driven for an extended period of time, the voltage to be applied to the scan electrodes during the write period except the period of scan pulse application is increased, thereby preventing the generation of unwanted discharge that can significantly degrade the display ON state (for example, refer to patent document 4).
Patent document 1: Japanese Unexamined Patent Publication (Kokai) No. 10-123998
Patent document 2: Japanese Unexamined Patent Publication (Kokai) No. 09-006283
Patent document 3: Japanese Unexamined Patent Publication (Kokai) No. 2003-015593
Patent document 4: Japanese Unexamined Patent Publication (Kokai) No. 2003-122296
The plasma display apparatus, which is a self-emissive display apparatus as earlier described, has a characteristic such that as the ratio (display ratio) of the ON display cells to the total number of cells of the panel increases, the power consumption increases because of the increase of the gas discharge current; in view of this, the increase of the power consumption is suppressed by employing a strategy such as reducing the frequency of the sustain voltage waveform as the display ratio increases.
This strategy, however, has a limitation from the standpoint of ensuring display quality, because reducing the frequency of the sustain voltage waveform leads to reducing the brightness of the display. That is, the frequency of the sustain voltage waveform cannot be reduced below a certain frequency, and as a result, a design that allows for a given consumption power value becomes necessary.
The driving circuits (drivers) where such power consumption occurs are the scan driver IC block (scan driver 4) on the scan electrode side and the individual driving circuit component block (X-common driver 5 and Y-common driver 6) on the common electrode side; accordingly, thermal design that provides these drivers with heat dissipation performance that allows for a certain amount of power consumption becomes necessary.
To compare the thermal design for the scan driver IC block with that for the driving circuit component block, the driving circuit component block comprises, for example, individual devices such as FETs and, since the device structure is simple, and the number of connecting terminals is small, a good thermal design can be achieved at low cost and in a relatively simple manner, while on the other hand, the scan driver IC block comprises, for example, a plurality of ICs having many terminals and mounted on a flexible substrate, and as a result, providing each IC with a uniform heat sinking structure relatively free from variation is costly as it requires a complex structure design. Therefore, it is desired to simplify the heat sinking structure as much as possible for the scan driver IC block. Needless to say, for the ICs used as the X-common driver 5, the Y-common driver 6, and the address driver 3 also, if a simple heat sinking design can suffice for the purpose, it would be the best.
Further, in the prior art, if the power for address driving can be reduced by controlling the address pulse application timing, the characteristic that peak power occurs, for example, when displaying a staggered dot pattern remains unaddressed. There is also employed a strategy that monitors the driving current or device temperature on the address electrode side and, when they increase, reduces the number of subframes, thereby equivalently reducing the address frequency to reduce the peak power, but this strategy is not so preferable from the standpoint of ensuring display quality because the grayscale rendition degrades when the number of subframes is reduced.
First, as shown in
The present inventors have discovered that there is a certain law between the panel temperature, the display ratio, and the driving voltage (maximum and minimum driving voltages) in the prior art plasma display apparatus such as shown in FIGS. 1 to 5. More specifically, it has been confirmed that, in the prior art plasma display apparatus such as shown in FIGS. 1 to 5, when the panel temperature rises, the driving voltage can be made lower than when the panel temperature is low and, when the display ratio increases, the driving voltage can be made lower than when the display ratio is low.
That is, among the state S1 in which the panel temperature is low and the display ratio is also low, the state S2 in which the panel temperature is high but the display ratio is low, the state S3 in which the panel temperature is low but the display ratio is high, and the state S4 in which the panel temperature is high and the display ratio is also high, it has been confirmed that when the panel temperature rises, the panel can be driven (the discharge can be produced) by a lower driving voltage and, when the display ratio increases, the panel can be driven (the discharge can be produced) by a lower driving voltage, as shown in
In
As shown in
In view of the problem associated with the prior art flat display panel described above, it is an object of the present invention to provide a flat display apparatus that can reduce the power consumption required for driving, while also achieving reductions in the size and cost of its associated circuit components, and a driving method for the same.
According to a first aspect of the present invention, there is provided a flat display apparatus having a flat display panel in which at least some of display electrodes are formed from a scan electrode and an address electrode arranged so as to intersect each other; a scan driver which is connected to the scan electrode and supplies a driving voltage waveform to the scan electrode; an address driver which is connected to the address electrode and supplies a driving voltage waveform to the address electrode; and a control circuit which controls operation of driving circuits in the flat display panel, the driving circuits including the scan driver and the address driver, wherein the flat display apparatus comprises a driving load detecting unit detecting an amount of driving load for the scan driver or the address driver; and a driving voltage varying unit varying, based on the detected amount of driving load, a driving voltage for the scan electrode or a driving voltage for the address electrode.
According to a second aspect of the present invention, there is provided a flat display apparatus having a flat display panel in which at least some of display electrodes are formed from a scan electrode and an address electrode arranged so as to intersect each other; a scan driver which is connected to the scan electrode and supplies a driving voltage waveform to the scan electrode; an address driver which is connected to the address electrode and supplies a driving voltage waveform to the address electrode; and a control circuit which controls operation of driving circuits in the flat display panel, the driving circuits including the scan driver and the address driver, wherein the flat display apparatus comprises a panel temperature detecting unit detecting the temperature of the flat display panel; and a driving voltage varying unit varying, based on the detected temperature of the flat display panel, a driving voltage for the scan electrode or a driving voltage for the address electrode.
According to a third aspect of the present invention, there is provided a flat display apparatus having a flat display panel in which at least some of display electrodes are formed from a scan electrode and an address electrode arranged so as to intersect each other and a common electrode as a sustain electrode arranged in parallel to the scan electrode; a scan driver which is connected to the scan electrode and supplies a driving voltage waveform to the scan electrode; an address driver which is connected to the address electrode and supplies a driving voltage waveform to the address electrode; a common electrode driver which is connected to the common electrode and supplies a driving voltage waveform to the common electrode; and a control circuit which controls operation of driving circuits in the flat display panel, the driving circuits including the scan driver, the address driver, and the common electrode driver, wherein the flat display apparatus comprises a driving load detecting unit detecting an amount of driving load for the scan driver, the address driver, or the common electrode driver; and a driving voltage varying unit varying, based on the detected amount of driving load, a driving voltage for the scan electrode, a driving voltage for the address electrode, or a driving voltage for the common electrode driver.
According to a fourth aspect of the present invention, there is provided a flat display apparatus having a flat display panel in which at least some of display electrodes are formed from a scan electrode and an address electrode arranged so as to intersect each other and a common electrode as a sustain electrode arranged in parallel to the scan electrode; a scan driver which is connected to the scan electrode and supplies a driving voltage waveform to the scan electrode; an address driver which is connected to the address electrode and supplies a driving voltage waveform to the address electrode; a common electrode driver which is connected to the common electrode and supplies a driving voltage waveform to the common electrode; and a control circuit which controls operation of driving circuits in the flat display panel, the driving circuits including the scan driver, the address driver, and the common electrode driver, wherein the flat display apparatus comprises a panel temperature detecting unit detecting the temperature of the flat display panel; and a driving voltage varying unit varying, based on the detected temperature of the flat display panel, a driving voltage for the scan electrode, a driving voltage for the address electrode, or a driving voltage for the common electrode driver.
According to a fifth aspect of the present invention, there is provided a driving method for a flat display apparatus that comprises a flat display panel in which at least some of display electrodes are formed from a scan electrode and an address electrode arranged so as to intersect each other, the flat display apparatus having a characteristic such that as the amount of driving load of the flat display panel increases, activation energy of discharge gas increases and a driving voltage decreases, wherein the method is characterized in that when the amount of driving load of the flat display panel increases, the driving voltage of the scan electrode or the address electrode is reduced.
According to a sixth aspect of the present invention, there is provided a driving method for a flat display apparatus that comprises a flat display panel in which at least some of display electrodes are formed from a scan electrode and an address electrode arranged so as to intersect each other, the flat display apparatus having a characteristic such that as the temperature of the flat display panel rises, activation energy of discharge gas increases and a driving voltage decreases, wherein the method is characterized in that when the temperature of the flat display panel rises, the driving voltage of the scan electrode or the address electrode is reduced.
According to a seventh aspect of the present invention, there is provided a driving method for a flat display apparatus that comprises a flat display panel in which at least some of display electrodes are formed from a scan electrode and an address electrode arranged so as to intersect each other and a common electrode as a sustain electrode arranged in parallel to the scan electrode, the flat display apparatus having a characteristic such that as the amount of driving load of the flat display panel increases, activation energy of discharge gas increases and a driving voltage decreases, wherein the method is characterized in that when the amount of driving load of the flat display panel increases, the driving voltage of the scan electrode, the address electrode, or the common electrode is reduced.
According to an eighth aspect of the present invention, there is provided a driving method for a flat display apparatus that comprises a flat display panel in which at least some of display electrodes are formed from a scan electrode and an address electrode arranged so as to intersect each other and a common electrode as a sustain electrode arranged in parallel to the scan electrode, the flat display apparatus having a characteristic such that as the temperature of the flat display panel rises, activation energy of discharge gas increases and a driving voltage decreases, wherein the method is characterized in that when the temperature of the flat display panel rises, the driving voltage of the scan electrode, the address electrode, or the common electrode is reduced.
According to the present invention, it becomes possible to provide a flat display apparatus that can reduce the power consumption required for driving, while also achieving reductions in the size and cost of its associated circuit components by simplifying their heat sinking structures, and a driving method for such a flat display apparatus.
As is apparent from a comparison of
As shown in
The reason that the scan driver 4 provided with the temperature sensor is not provided with a current sensor is that the current is consumed primarily by the Y-common driver 6 that performs sustain discharge, while the temperature rise occurs primarily in the scan driver 4. Of course, each driver (driver IC) may be provided with both the temperature sensor and the current sensor, but various modifications can be made as required; for example, the current sensor may not be provided, but only the temperature sensor may be provided, or the temperature sensor may be provided only for a specific driver IC (for example, the address driver IC).
The data (temperature information and current information) measured by the temperature sensors and current sensors provided for the respective drivers are sent to the control circuit 2 which computes the amount of driving load of each driver from the measured data. Here, the amount of driving load can also be obtained directly from the actual display image data (DATA). The temperature of the plasma display panel 1 is measured by the temperature sensor 101 attached, for example, to the rear metal plate of the panel, and the panel temperature information is sent to the control circuit 2.
Then, as will be described below, control is performed to drive the panel (produce a discharge) by reducing the driving voltage as the panel temperature rises and to drive the panel (produce a discharge) by reducing the driving voltage as the display ratio increases.
As shown in
As previously described with reference to
The optimum value of the driving voltage is also influenced by the number of cells that are turned on within the plasma display panel, i.e., the ratio (display ratio) of the number of cells caused to emit light by glow discharge to the total number of cells; that is, as the display ratio increases, the number of electrons or ions in the discharge gas space increases, making it easier to produce a discharge, and the required driving voltage thus tends to decrease and, conversely, as the display ratio decreases, the number of electrons or ions in the discharge gas space decreases, making it difficult to produce a discharge, and the required driving voltage thus tends to increase.
As is apparent from a comparison of
More specifically, as shown in
In
As is apparent from a comparison of
Embodiments of the flat display apparatus according to the present invention and the driving method for the same will be described in detail below with reference to the accompanying drawings.
As shown in
For the states S1 to S4, the panel temperature can be detected directly by disposing a temperature detecting device such as a thermistor (for example, the temperature sensor 101 in
On the other hand, the display ratio can be detected directly by counting the number of pieces of input display image data, or indirectly by detecting the sustain current value supplied from the sustain supply voltage (for example, by the current sensors 501 and 601 in
In accordance with the thus obtained panel temperature and display ratio, the applicable state during the panel driving is determined from among the states S1 to S4, and the address-pulse voltage Va is varied to match the determined state. Here, it will be appreciated that control may be performed by setting a larger number of states by combining the panel temperature and the display ratio. Alternatively, in order to simply the detection system or the control circuit, provisions may be made to determine the various states based only on the panel temperature or the display ratio; in that case also, the intended object can, of course, be accomplished.
In this way, according to the first embodiment of the flat display apparatus, the power requirements of the address driving power supply can be reduced, while also reducing the power consumption of the address driver IC itself; this serves to simplify the heat sink mounting structure for the address driver IC and to reduce the size and cost of its associated components.
As shown in
As shown in
In addition to offering the same effect as that achieved by the second embodiment, the third embodiment of the flat display apparatus is effective when there is a limit to the withstanding voltage of the scan driver IC or when a pulse greater than the withstanding voltage of the scan driver IC is output.
As shown in
The fourth embodiment of the flat display apparatus shows the case where the voltage is divided between the address driver side and the scan driver side while keeping the magnitude of the overall write-pulse voltage unchanged.
First, the state in which the amount of driving load of the address driver IC is approximately equal to that of the scan driver IC is chosen as the normal state and, in this normal state, the address voltage Va is generally set lower and the scan voltage Vy higher. The reason is that, in an ordinary display pattern, the driving on the scan electrode side is performed only once during the scanning of one screen, while on the other hand, the driving on the address side is performed a plurality of times corresponding to the scan driving of the plurality of scan electrodes, and as a result, the address driving frequency is higher and the power consumption on the address side tends to increase. Therefore, the address voltage Va is set lower and the scan voltage Vy higher because of the need to maintain a power consumption balance between the address driver side and the scan driver side. Here,
When the amount of driving load of the scan driver IC has relatively increased from the normal state, the scan voltage −Vy is reduced, and the address voltage Va is increased correspondingly.
Conversely, when the amount of driving load of the address driver IC has relatively increased from the normal state, the address voltage Va is reduced, and the scan voltage −Vy is increased correspondingly.
According to the flat panel display of the fourth embodiment, a well balanced heat sink design can be achieved for both the address driver IC and the scan driver IC.
As shown in
As shown in
According to the sixth embodiment of the flat display apparatus, the heat sink mounting structure for the scan driver IC can be simplified.
As shown in
According to the seventh embodiment of the flat display apparatus, an optimum total design can be accomplished that achieves a well balanced mounting structure for the common sustain electrode driving circuit (X-common driver circuit) as well as for the scan driver IC.
In
That is, by setting the pulse width of the drive pulse wider, the panel can be driven even if the discharge delay time of the gas discharge in the display pixel (cell) becomes longer; accordingly, by setting the pulse width wider while reducing the driving voltage as the state changes from S1 toward S4, the driving voltage can be further reduced compared with the case explained with reference to
In the eighth embodiment of the flat display apparatus shown in
In the ninth embodiment of the flat display apparatus shown in
As shown in
The 10th embodiment of the flat display apparatus offers the effect that the address-pulse voltage can be reduced in a concentrated and reliable manner.
As shown in
In the above-described 11th embodiment of the flat display apparatus, the sustain pulse width was simply varied, but in the 12th embodiment of the flat display apparatus shown in
According to the 12th embodiment of the flat display apparatus, variations including the variation of the sustain pulse can be addressed in a further reliable manner.
As shown in
More specifically, in the 13th embodiment of the flat display apparatus, when the amount of driving load of the address driver IC increases, or when the panel-temperature/display-ratio state transitions toward S4, the reset-pulse voltage is increased to generate a larger amount of initial wall charge, but conversely, when the amount of driving load of the address driver IC decreases, or when the panel-temperature/display-ratio state transitions toward S1, the reset-pulse voltage is reduced to generate a smaller amount of initial wall charge.
In this way, in the reset period TR, when the amount of driving load of the address driver IC increases, or when the panel-temperature/display-ratio state transitions toward S4, the reset-pulse voltage is increased to generate a larger amount of initial wall charge, thereby making it easier for the write discharge to occur in the subsequent address period TA and thus equivalently reducing the required write-pulse voltage. By performing the above operation when the amount of driving load of the address driver IC increases or when the panel-temperature/display-ratio state transitions toward S4, the address-pulse voltage can be set lower.
The amount of initial wall charge can be controlled not only by controlling the reset-pulse voltage but also by controlling the pulse width of the reset pulse, and the amount of initial wall charge can also be increased by increasing the pulse width.
As shown in
FIGS. 25 to 27 are diagrams for explaining a 15th embodiment of the flat display apparatus according to the present invention, and show examples of driving waveforms when the various methods of control are combined, that is, the driving voltage is controlled in accordance with the panel temperature and display ratio states as explained with reference to
That is, in the 15th embodiment of the flat display apparatus, the amount of driving load of the address driver IC is compared with that of the scan driver IC and, based on the result of the comparison, the driving waveform is controlled in the following manner.
First, when the amount of driving load of the address driver IC is approximately equal to that of the scan driver IC, the voltages of all the drive pulses, such as the reset pulse, the write pulse, and the sustain pulse, and their pulse widths are set to well balanced average values, as shown in
When the amount of driving load of the scan driver IC increases from the above average state and becomes higher than that of the address driver IC, the scan electrode (Y electrode) and common electrode (X electrode) sustain-pulse voltages are reduced, while increasing their pulse widths, as shown in
On the other hand, when the amount of driving load of the address driver IC increases from the above average state and becomes higher than that of the scan driver IC, the address-pulse voltage is reduced, while increasing its pulse width, as shown in
According to the 15th embodiment of the flat display apparatus, both the address driver IC and the scan driver IC need only be designed to handle average loads and need not be designed to handle excessive loads and, as a whole, the size and cost of the apparatus can be reduced.
While each of the above embodiments has been described in detail by primarily taking as an example the three-electrode surface-discharge AC-driven type plasma display apparatus, it will be appreciated that the present invention can be widely applied to flat display apparatus having such characteristics that the panel driving voltage decreases as the data display ratio or the panel temperature increases, not to mention two-electrode AC-driven type plasma display apparatus that utilize the gas discharge phenomenon. In particular, the present invention offers a great effect when applied to a flat display apparatus that is self-emissive and that consumes relatively large power.
As described above, according to the present invention, the power consumption of the driving circuits (driver ICs) for driving the display electrodes of a flat display panel can be reduced, while equalizing the power consumption between the respective driving circuits, and the design of each driving circuit, in particular, the heat sink design, can be simplified, achieving reductions in the overall size and cost of the apparatus.
The present invention can be widely applied to flat display apparatus, particularly to display apparatus for personal computers, workstations, etc. and other flat display apparatus such as plasma display apparatus that are self-emissive, can achieve a large-screen display, and consume relatively large power and that are used as hang-on-the-wall televisions or as apparatus for displaying advertisements, information, etc.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2004-229474 | Aug 2004 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP05/07044 | 4/11/2005 | WO | 11/30/2006 |
