Claims
- 1. An improved field emission display comprising:
- multiple row address lines;
- multiple column address lines;
- said row address lines intersecting said column address lines, with the intersection of a single row address line with a single column address line being associated with a single pixel within said display;
- a grid which is common to the entire display, and which is held at a first potential;
- a plurality of pixels, wherein each pixel includes
- a group of field emission cathodes, wherein connecting the cathodes to a potential sufficiently low relative to said first potential will induce field emission;
- a logical AND gate circuit having an output and first and second inputs for receiving first and second input signals, respectively, one of said inputs being coupled to that pixel's respective row address line, and the other input being coupled to that pixel's column address line, wherein the logical AND gate circuit produces at its output a signal which is a logical AND of the first and second input signals;
- a first transistor having gate, drain, and source terminals, the gate being connected to the output of the gate circuit, and the drain being connected to the field emission cathodes in said group: and
- a resistance connected between a second potential and the source terminal of the first transistor, the second potential being less than said potential sufficient to induce field emission.
- 2. The improved field emission display of claim 1, wherein said second potential is ground potential.
- 3. The improved field emission display of claim 1, wherein said logical AND gate circuit comprises a second transistor having gate, source, and drain terminals, the gate of the second transistor being connected to the first input of the gate circuit, the source of the second transistor being connected to the second input of the gate circuit, and the drain of the second transistor being connected to the output of the gate circuit.
- 4. The improved field emission display of claim 3, wherein said logical AND gate circuit further comprises a capacitor coupled between said second potential and the gate of the first transistor.
- 5. The improved field emission display of claim 4, wherein the capacitor is included within the first transistor as parasitic capacitance of the gate of the first transistor.
- 6. A field emission display comprising:
- a voltage source for providing a voltage between a positive terminal and a negative terminal;
- a grid having a number of apertures, the grid being connected to the positive terminal of the voltage source;
- a plurality of row address lines;
- a plurality of column address lines;
- said row address lines intersecting said column address lines, with the intersection of a single row address line with a single column address line being associated with a single pixel within said display;
- a plurality of pixels, wherein each pixel includes
- a number of field emitters, each field emitter being positioned adjacent an aperture of the grid;
- a gating circuit having an output and first and second inputs for receiving first and second input signals, respectively, one of said inputs being coupled to that pixel's associated row address line, and the other input being coupled to that pixel's associated column address line, wherein the gating circuit connects or disconnects the second input signal to the output in response to whether the first input signal is high or low;
- a first transistor having gate, drain, and source terminals, the gate being connected to the output of the gating circuit of the pixel, and the drain being connected to the field emitters of the pixel; and
- an electrical resistance connected between the negative terminal of the voltage source and the source terminal of the first transistor of the pixel.
- 7. A field emission display comprising:
- a voltage source for providing a voltage between a positive terminal and a negative terminal;
- a grid having a number of apertures, the grid being connected to the positive terminal of the voltage source;
- a plurality of row address lines;
- a plurality of column address lines;
- said row address lines intersecting said column address lines, with the intersection of a single row address line with a single column address line being associated with a single pixel within said display;
- a plurality of pixels, wherein each pixel includes
- a number of field emitters, each field emitter being positioned adjacent an aperture of the grid;
- a first transistor having gate, drain, and source terminals, the drain being connected to the field emitters of the pixel; and
- an electrical resistance connected between the negative terminal of the voltage source and the source terminal of the first transistor of the pixel; and
- a second transistor having gate, source and drain terminals, the gate of the second transistor being connected to one of either the column address line or the row address line associated with that particular pixel, the source of the second transistor being connected to the other one of said column address line or row address line associated with that pixel, and the drain of the second transistor being connected to the gate of the first transistor of the pixel.
- 8. A display according to claim 7, wherein each pixel further comprises a capacitor connected between the gate of the first transistor of the pixel and the negative terminal of the voltage source.
- 9. A display according to claim 8, wherein the capacitor in each pixel is included within the first transistor of the pixel as parasitic capacitance of the gate of the first transistor of the pixel.
- 10. Apparatus for controlling the current through a number of field emitters, comprising:
- a voltage source for providing a voltage between a positive terminal and a negative terminal;
- a grid having a number of apertures, the grid being connected to the positive terminal of the voltage source;
- a number of field emitters, each field emitter being positioned adjacent an aperture of the grid;
- a first transistor having a source, drain, and gate, the drain of the first transistor being connected to the field emitters;
- an electrical resistance connected between the source of the first transistor and the negative terminal of the voltage source; and
- a circuit for applying a control voltage to the gate of the first transistor.
- 11. Apparatus according to claim 10, further comprising a capacitor connected between the gate of the first transistor and the negative terminal of the voltage source.
- 12. Apparatus according to claim 10, wherein the circuit for applying a control voltage to the gate of the first transistor comprises:
- a second transistor having a gate and a channel, wherein
- the channel of the second transistor is connected between the gate of the first transistor and a first input voltage, and
- the gate of the second transistor is connected to receive a second input voltage.
- 13. Apparatus according to claim 12, further comprising a capacitor connected between the gate of the first transistor and the negative terminal of the voltage source.
- 14. A field emission display, comprising:
- a voltage source for providing a voltage between a positive terminal and a negative terminal;
- a grid having a number of apertures, the grid being connected to the positive terminal of the voltage source;
- a plurality of row address signal lines, wherein each respective row address line carries a respective row address electrical signal;
- a plurality of column address signal lines, wherein each respective column address line carries a respective column address electrical signal, and wherein the column address lines intersect the row address lines; and
- a plurality of pixels, each pixel being associated with one of the row address lines and one of the column address lines, wherein each pixel is associated with a corresponding pixel circuit which includes
- a number of field emitters, each field emitter being positioned adjacent an aperture of the grid,
- a first transistor having a source, drain, and gate, the drain of the first transistor of the pixel being connected to the field emitters of the pixel,
- an electrical resistance connected between the source of the first transistor of the pixel and the negative terminal of the voltage source, and
- a control circuit for supplying to the gate of the first transistor of the pixel a voltage responsive to the signal on one of the address lines associated with the pixel.
- 15. A display according to claim 14, wherein each pixel further comprises a capacitor connected between the gate of the first transistor of the pixel and the negative terminal of the voltage source.
- 16. A display according to claim 14, wherein the control circuit of each pixel comprises:
- a logical AND gate circuit having an output and having first and second inputs for receiving first and second input signals, respectively, one of said inputs being coupled to the row address line associated with the pixel, and the other input being coupled to the column address line associated with the pixel, wherein the logical AND gate circuit produces at its output a signal which is a logical AND of the first and second input signals.
- 17. A display according to claim 16, wherein each pixel further comprises a capacitor connected between the gate of the first transistor of the pixel and the negative terminal of the voltage source.
- 18. A display according to claim 14, wherein the control circuit of each pixel comprises:
- a second transistor having a gate and a channel, wherein
- the channel of the second transistor of the pixel is connected between the gate of the first transistor of the pixel and one of the two address lines associated with the pixel, and
- the gate of the second transistor is connected to the other one of the two address lines associated with the pixel.
- 19. A display according to claim 18, wherein each pixel further comprises a capacitor connected between the gate of the first transistor of the pixel and the negative terminal of the voltage source.
- 20. A field emission display, comprising:
- a first voltage source for providing a first voltage between a positive terminal and a negative terminal;
- a grid having a number of apertures, the grid being connected to the positive terminal of the voltage source;
- a plurality of row address signal lines;
- a plurality of column address signal lines, wherein the column address lines intersect the row address lines; and
- a plurality of pixels, each pixel being associated with one of the row address lines and one of the column address lines, wherein each pixel is associated with a corresponding pixel circuit which includes
- a number of field emitters, each field emitter being positioned adjacent an aperture of the grid,
- a first transistor having a gate, a source, and a drain, the source of the first transistor being connected to the negative terminal of the first voltage source, and the drain of the first transistor being connected to the field emitters of the pixel,
- a second transistor having a gate and a channel, the gate of the second transistor being connected to the row address line associated with the pixel, and
- a third transistor having a gate and a channel, the gate of the third transistor being connected to the column address line associated with the pixel;
- wherein, within each pixel, the respective channels of the second and third transistors of the pixel are connected in series between the gate of the first transistor of the pixel and a second voltage which is positive relative to the negative terminal of the first voltage source.
- 21. A display according to claim 20, wherein each pixel further comprises:
- an electrical resistance connected between the gate of the first transistor of the pixel and the negative terminal of the first voltage source.
- 22. A display according to claim 20, wherein each pixel further comprises:
- an electrical resistance connected between the source of the first transistor of the pixel and the negative terminal of the first voltage source.
- 23. A field emission display, comprising:
- a first voltage source for providing a first voltage between a positive terminal and a negative terminal;
- a grid having a number of apertures, the grid being connected to the positive terminal of the voltage source;
- a plurality of row address signal lines;
- a plurality of column address signal lines, wherein the column address lines intersect the row address lines; and
- a plurality of pixels, each pixel being associated with one of the row address lines and one of the column address lines, wherein each pixel is associated with a corresponding pixel circuit which includes
- a number of field emitters, each field emitter being positioned adjacent an aperture of the grid,
- a first transistor having a gate, a source, and a drain, the gate of the first transistor being connected to a first input of the pixel, the source of the first transistor being connected to the negative terminal of the first voltage source, and the drain of the first transistor being connected to the field emitters of the pixel, and
- a second transistor having a gate, a source, and a drain, the gate of the second transistor being connected to a second input of the pixel, the source of the second transistor being connected to the negative terminal of the first voltage source, and the drain of the second transistor being connected to the gate of the first transistor of the pixel;
- wherein, within each pixel, one of the first and second inputs of the pixel is connected to the row address line associated with the pixel, and the other one of the first and second inputs of the pixel is connected to the column address line associated with the pixel.
- 24. A display according to claim 23, wherein:
- within each pixel, the address line connected to the first input of the pixel carries a logically inverted address signal, and the address line connected to the second input of the pixel carries a logically uninverted address signal.
- 25. A display according to claim 23, wherein each pixel further comprises:
- a diode connected between the first input of the pixel and the gate of the first transistor of the pixel.
- 26. A display according to claim 25, wherein the diode of each pixel is a third transistor having a source, a drain, and a gate, wherein the source of the third transistor is connected to the gate of the first transistor of the pixel, and wherein the drain and gate of the third transistor are connected to each other and to the first input of the pixel.
- 27. A method of controlling the current through a number of field emitters, comprising the steps of:
- supplying a voltage between a positive terminal and a negative terminal;
- providing a grid having a number of apertures;
- connecting the grid to the positive terminal;
- providing a number of field emitters
- positioning each field emitter adjacent an aperture of the grid;
- providing a first transistor having a source, drain, and gate;
- connecting the drain of the first transistor to the field emitters;
- connecting an electrical resistance between the source of the first transistor and the negative terminal of the voltage source; and
- applying a control voltage to the gate of the first transistor.
- 28. A method according to claim 27, further comprising the step of:
- connecting a capacitor between the gate of the first transistor and the negative terminal of the voltage source.
- 29. A method according to claim 27, wherein the step of applying a control voltage to the gate of the first transistor comprises:
- providing a second transistor having a gate and a channel;
- connecting the channel of the second transistor between the gate of the first transistor and a first input voltage; and
- applying a second input voltage to the gate of the second transistor.
- 30. A method according to claim 29, further comprising the step of:
- connecting a capacitor between the gate of the first transistor and the negative terminal of the voltage source.
- 31. A method of controlling a field emission display, comprising the steps of:
- providing a voltage between a positive terminal and a negative terminal;
- providing a grid having a number of apertures;
- connecting the grid to the positive terminal;
- providing a plurality of row address signal lines, wherein each respective row address line carries a respective row address electrical signal;
- providing a plurality of column address signal lines, wherein each respective column address line carries a respective column address electrical signal, and wherein the column address lines intersect the row address lines;
- providing a plurality of pixel circuits, each pixel circuit being associated with one of the row address lines and one of the column address lines;
- providing in each pixel circuit a number of field emitters;
- positioning each field emitter adjacent an aperture of the grid;
- providing in each pixel circuit a first transistor having a source, drain, and gate;
- connecting the drain of the first transistor of each pixel circuit to the field emitters of that pixel circuit;
- providing in each pixel circuit an electrical resistance;
- connecting the resistance of each pixel circuit between the source of the first transistor of that pixel circuit and the negative terminal; and
- applying to the gate of the first transistor of each pixel circuit a voltage responsive to the signal on one of the address lines associated with that pixel circuit.
- 32. A method according to claim 31, further comprising the steps of:
- providing a capacitor in each pixel circuit; and
- connecting the capacitor of each pixel circuit between the gate of the first transistor of that pixel circuit and the negative terminal.
- 33. A method according to claim 31, wherein the applying step comprises:
- providing in each pixel circuit a logical AND gate circuit having an output and having first and second inputs for receiving first and second input signals, respectively; and
- in each pixel circuit, coupling one of the inputs of the AND gate circuit of that pixel circuit to the row address line associated with that pixel circuit, and coupling the other input of said AND gate cicuit to the column address line associated with that pixel circuit.
- 34. A method according to claim 33, further comprising the steps of:
- providing a capacitor in each pixel circuit; and
- connecting the capacitor of each pixel circuit between the gate of the first transistor of that pixel circuit and the negative terminal.
- 35. A method according to claim 31, wherein the applying step comprises:
- providing in each pixel circuit a second transistor having a gate and a channel; and
- in each pixel circuit, connecting the channel of the second transistor of that pixel circuit between the gate of the first transistor of that pixel circuit and one of the two address lines associated with that pixel circuit, and connecting the gate of the second transistor of that pixel circuit between the other one of the two address lines associated with the pixel circuit.
- 36. A method according to claim 35, further comprising the steps of:
- providing a capacitor in each pixel circuit; and
- connecting the capacitor of each pixel circuit between the gate of the first transistor of that pixel circuit and the negative terminal.
Parent Case Info
This application is a continuation of application Ser. No. 08/530,562 filed Sep. 19, 1995 now U.S. Pat. No. 5,616,991; which is a continuation of application Ser. No. 08/209,579 filed Mar. 11, 1994, now abandoned; which is a continuation-in-part of application Ser. No. 08/011,927 that was filed on Feb. 1, 1993, now U.S. Pat. No. 5,357,172, which in turn, is a continuation-in-part of application Ser. No. 07/864,702 that was filed on Apr. 7, 1992 and is now issued U.S. Pat. No. 5,210,472.
This application also is a continuation-in-part of application Ser. No. 08/458,853 filed Jun. 2, 1995 by Lee et al, now U.S. Pat. No. 5,638,086; which is a continuation of application Ser. No. 08/138,535 filed Oct. 15, 1993, now abandoned; and which is a continuation-in-part of application Ser. No. 08/077,181 filed Jun. 15, 1993, now U.S. Pat. No. 5,410,218. This application also is a continuation-in-part of copending application Ser. No. 08/311,971 filed Sep. 26, 1994 by Hush et al., which is a continuation of application Ser. No. 08/060,111 filed May 11, 1993, now abandoned. This application also is a continuation-in-part of copending application Ser. No. 08/582,381 filed Jan. 11, 1996, which is a continuation of Ser. No. 08/305,107 filed Sep. 13, 1994 by Hush et al., now abandoned, which is a continuation of application Ser. No. 08/102,598 filed Aug. 5, 1993, now abandoned, which is a continuation-in-part of application Ser. No. 08/060,111 filed May 11, 1993, now abandoned.
US Referenced Citations (24)
Related Publications (2)
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Continuations (6)
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Continuation in Parts (3)
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