Patent Application
20140122552
The invention relates generally to a transceiver and, more particularly, to a physical transceiver (PHY) having a flexible architecture.
Turning to
Of interest here, however, are PHYs 110-1 to 110-N, and, as can be seen in greater detail in
As can be seen in
Of interest here are the scrambler 308 and descrambler 314. In this example, the scrambler 308 and descrambler 314 are able to perform data scrambling/descrambling and error checking One purpose in scrambling/descrambling data with the PHYs 110-1 to 110-N is to substantially randomize the data to reduce the impact of electromagnetic interference (EMI) and improve signal integrity. This is typically accomplished by the use of a pseudorandom bit sequence (PRBS) generated with a specified polynomial. For example, for 8b/10b encoding, a PRBS-7 (or 1+x6+x7) can be employed, and, for synchronous optical networking or SONET (as specified in ITU 0.150), PRBS-23 (or X23+X18+1). Similarly, this PRBS signaling can be employed for error checking.
However, as demonstrated above, one polynomial is generally not applicable to all standards (e.g., 802.3-2008 and SONET); each standard usually specifies its own polynomial. Conventionally, this meant that each PHY (e.g., 110-1) would be designed for a particular standard (e.g., PRBS-7 for 802.3-2008) and would lack the flexibility to be used with other standards. A reason for this is that the serial and parallel implementations for the PHYs (e.g., 110-1) would be too costly in terms of area, price, and power consumption to be generally applicable.
Therefore, there is a need for a flexible transceiver architecture.
Some examples of conventional systems are: U.S. Pat. Nos. 4,744,104; 5,267,316; 6,820,230; 6,907,062; 7,124,158; 7,414,112; 7,486,725; 7,505,589; U.S. Patent Pre-Grant Publ. No. 2003/0014451; U.S. Patent Pre-Grant Publ. No. 2007/008997; and U.S. Patent Pre-Grant Publ. No. 2007/0098160.
In accordance with an embodiment of the present invention, an apparatus is provided. The apparatus comprises a polynomial register having a plurality of bits, wherein the polynomial register is configured to store a user-defined polynomial; a first bus; a second bus; a transceiver that is coupled to the first bus, the second bus, and the polynomial register, wherein the transceiver includes: a pseudorandom bit sequence (PRBS) generator is configured to generate a scrambled signal from the user-defined polynomial; and a PRBS checker that is configured to generate a descrambled signal from a second signal using the user-defined polynomial.
In accordance with an embodiment of the present invention, the first bus further comprises a first input bus and a second input bus, and wherein the second bus further comprises a first output bus and a second output bus, and wherein the PRBS generator is coupled of the first output bus, and wherein the PRBS checker is coupled to the second input bus.
In accordance with an embodiment of the present invention, the first input bus has a programmable width.
In accordance with an embodiment of the present invention, the PRBS checker further comprises: a first matrix circuit that is configured to include a first matrix corresponding to the user-defined polynomial; a second matrix circuit that is configured to include a first matrix corresponding to the user-defined polynomial; a first multiplier that is coupled to the second matrix circuit and that is coupled to the respective one of the encoder and the second input bus; a data register that is coupled to the second input bus; a second multiplier that is coupled to the first matrix circuit and the data register; an XOR circuit that is coupled to the first and second multipliers; and an error counter that is coupled to the XOR circuit.
In accordance with an embodiment of the present invention, the data register further comprises a first data register, and wherein the PRBS generator further comprises: a third matrix circuit that is configured to include a third matrix corresponding to the user-defined polynomial; a third multiplier that is coupled to the third matrix circuit; a first multiplexer that is coupled to the third multiplier and that is configured to receive a seed; a second data register that is coupled to the first multiplexer and the second data register.
In accordance with an embodiment of the present invention, the transceiver further comprises a detector that is coupled to the PBRS generator and the PRBS checker.
In accordance with an embodiment of the present invention, the polynomial register has 32 bits.
In accordance with an embodiment of the present invention, an apparatus is provided. The apparatus comprises a media access control (MAC) circuit; a interface that is coupled to the MAC circuit; a physical transceiver (PHY) having: a polynomial register having a plurality of bits, wherein the polynomial register is configured to store a user-defined polynomial; a first bus that is coupled to the interface; a second bus; a transceiver that is coupled to the first bus, the second bus, and the polynomial register, wherein the transceiver includes: a pseudorandom bit sequence (PRBS) generator is configured to generate a scrambled signal from the user-defined polynomial; and a PRBS checker that is configured to generate a descrambled signal from a second signal using the user-defined polynomial.
In accordance with an embodiment of the present invention, the PHY further comprises a detector that is coupled to the PBRS generator and the PRBS checker.
In accordance with an embodiment of the present invention, the apparatus further comprise a communications medium that is coupled to the PHY.
In accordance with an embodiment of the present invention, the detector is configure use the PRBS generator and the PRBS checker to characterize the communications medium.
In accordance with an embodiment of the present invention, the apparatus further comprises a host that is coupled to the MAC circuit.
In accordance with an embodiment of the present invention, a method is provided. the method comprises retrieving a user-defined polynomial from a polynomial register having a plurality of bits; generating first, second, and third matrices based at least in part on the user-defined polynomial; generating a first PRBS data set using the first matrix; transmitting the first PRBS data set over a communications medium; receiving a second PRBS data set over the communications medium; and determining a number of bit errors with the second PRBS data set using the second and third matrices.
In accordance with an embodiment of the present invention, the method further comprises: adjusting the first PRBS data set; and repeating the steps of transmitting, receiving, and determining.
In accordance with an embodiment of the present invention, the method further comprises characterizing the communication channel based at least in part on the number of bit errors.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views.
Turning to
Turning to
Also, as can be seen in the example of
Thus, for an example register (e.g., 601) having a width of 32 bits, the user can specify any of approximately 2×109 polynomials. This user-defined polynomial (which can be retrieved from register 601) can be used by the scrambler 502, PRBS generator 504, descrambler 506, and PRBS checker 508 accordingly. Alternatively, there can be multiple polynomial registers (e.g. 510), and each of the scrambler 502, PRBS generator 504, descrambler 506, and PRBS checker 508 may have a separate polynomial register (e.g., 510).
Turning to
The PRBS system (e.g., PRBS generator 504 and PRBS checker 506) in this example is based in part on the generation of polynomial state and data matrices (which can respectively be referred to as the P-matrix and D-matrix). In operation, the signal POLY (which generally corresponds to the user-defined polynomial stored in register 510) can be used to generate matrices, which can be referred to. The P- and D-matrices P and D are typically square binary matrices that are a function of or based at least in part on the user-defined polynomial. The basis for forming the P- and D-matrices P and D are identity matrices IP and ID (respectively), which typically have uniquely assigned vectors for each column of the first row of the P- and D-matrices P and D (i.e., P0,j and D0,j). An example of identity matrix IP can be seen below:
The identity matrix ID is generally comprised of the matrix IP that is shifted or adjusted based on the desired input bus width. For example, the identity matrix ID (which is derived from the matrix IP shown above) can be as follows for a 20-bit bus width:
An adjustment vector {right arrow over (A)} is also determined. Typically, when the signal POLY1 is transmitted, the lowest bit is truncated, and a ‘0’ is appended to signal POLY1 to form adjustment vector {right arrow over (A)}. For example, with the PRBS-7 polynomial used above, the adjustment vector A would be:
The P- and D-matrices P and D can then be determined.
Looking first to the P-matrix P, it can be determined on a row-by-row basis through the use of a set of matrices (e.g., 32-32×32 matrices), which can be referred to a working matrices WPM[r], where r denote the P-matrix P row. These working matrices WP[r], in this example, are based at least in part on the identity matrix IP and can be determined using the following formula:
where
FNP[r]=({right arrow over (WPj[r−1])}⊕{right arrow over (A)})· . . . ·({right arrow over (WP0[r−1])}⊕{right arrow over (A)}) (2)
The P-matrix P can then be extracted from working matrices WP[r] by application of the following equation:
where BW is the bus width. For example, with the PRBS-7 polynomial used above and a 20-bit bus width BW, the P-matrix P should be:
Similarly, with D-matrix D, it can be determined on a row-by-row basis through the use of a set of matrices (e.g., 32-32×32 matrices) or working matrices WD[r]. These working matrices WD[r], in this example, are based at least in part on the identity matrix ID and can be determined using the following formula:
where
FND[r]=({right arrow over (WDj[r−1])}⊕{right arrow over (A)})· . . . ·({right arrow over (WD0[r−1])}⊕{right arrow over (A)}) (5)
The D-matrix D can then be extracted from working matrices WD[r] by application of the following equation:
Looking first to the PRBS generator 504, it does not rely on a D-matrix. As shown in
The PRBS checker 508, on the other hand, does use both the P- and D-matrices P and D and has a function that is similar to the descrambler 506. In operation, the P- and D-matrices P and D are generated by matrix circuits 702 and 704, respectively, the input data DATAIN for checker 508. This input data DATAIN can also be written to register 710. The multiplier 606 can multiply the input data DATAIN (which can for example be 20-bits wide data vector) by the D-matrix D. The P-matrix P can be multiplied by the information (e.g., vector) stored in register 710 with multiplier 712. The outputs of multipliers 706 and 712 can then be XORed with circuit 708 and output to error counter 718 that generates an error count value ECNT and an error flag ERRORFLG. Alternatively, an inverse of the input data DATAIN when the multiplexer is selected to pass the output of inversion circuit 714; this is typically employed when the generator 504 is selected to output an inverted data vectors (e.g., DATAOUT).
One advantage of having such a flexible PRBS system is that the communication channel can be characterized or optimized. For example, a detector 512 can be included that can control the generator 504 and checker 506. This detector 512 can allow for iterative or repeated PRBS transmission over the communication channel, and, based on the error, adjustments can be made so as to substantially optimize transmission over the communication channel. Alternatively, this detector 512 can be used to determine the type of communication channel (e.g., optical, twisted pair, and so forth) using similar repeated transmissions.
Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.
