Patent Application
20080043563
One or more aspects of the present invention are particularly pointed out and distinctly claimed as examples in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
In accordance with an aspect of the present invention, data is transferred between input/output (I/O) devices and memory (e.g., noncontiguous (i.e., not physically contiguous) main storage, expanded storage, main memory, random access memory, or any other storage directly accessible by the central processing unit) irrespective of memory boundaries. For instance, the data need not be transferred on 2 KB or 4 KB byte boundaries. Instead, modified indirect data addressing is employed enabling data to be transferred under control of control blocks, referred to herein as modified indirect data address words (MIDAWs). Control is passed from one MIDAW to another MIDAW, in response to the amount of data specified for transfer in the one MIDAW, and assuming there is more data to transfer. The passing of control occurs independent of a memory boundary (e.g., 2 KB, 4 KB) providing flexibility in controlling data transfers.
This flexible data transfer control is usable in a number of environments, including, but not limited to, processing environments having input/output subsystems, such as channel subsystems, offered by International Business Machines Corporation, Armonk, N.Y.
One example of a processing environment incorporating and using one or more aspects of the present invention is described with reference to
Main memory 102 stores data and programs, which are input from input devices 112. Main memory 102 is directly addressable and provides for high-speed processing of data by central processing units 104 and channel subsystem 108. In one example, main memory 102 includes a customer area and a system area (not shown).
Central processing unit 104 is the controlling center of environment 100. It contains the sequencing and processing facilities for instruction execution, interruption action, timing functions, initial program loading, and other machine-related functions. Central processing unit 104 is coupled to storage control element 106 via a connection 114, such as a bidirectional or unidirectional bus.
Storage control element 106 is coupled to main memory 102 via a connection 116, such as a bus, central processing units 104 via connection 114 and channel subsystem 108 via a connection 118, e.g., a double word bus. Storage control element 106 controls, for example, the queuing and execution of requests made by CPU 104 and channel subsystem 108.
Channel subsystem 108 is coupled to storage control element 106, as described above, and to each of the control units via a connection 120, such as a serial link. Channel subsystem 108 directs the flow of information between input/output devices 112 and main memory 102. It relieves the central processing units of the task of communicating directly with the input/output devices and permits data processing to proceed concurrently with input/output processing. The channel subsystem uses one or more channel paths 122 as the communication links in managing the flow of information to or from input/output devices 112. As a part of the input/output processing, channel subsystem 108 also performs the path-management functions of testing for channel path availability, selecting an available channel path and initiating execution of the operation with the input/output devices.
Each channel path 122 includes a channel 124 (channels are located within the channel subsystem, in one example, as shown in
Also located within channel subsystem 108 are subchannels (not shown). One subchannel is provided for and dedicated to each input/output device accessible to a program through the channel subsystem. A subchannel (e.g., a data structure, such as a table) provides the logical appearance of a device to the program. Each subchannel provides information concerning the associated input/output device 112 and its attachment to channel subsystem 108. The subchannel also provides information concerning input/output operations and other functions involving the associated input/output device. The subchannel is the means by which channel subsystem 108 provides information about associated input/output devices 112 to central processing units 104, which obtain this information by executing input/output instructions.
Channel subsystem 108 is coupled to one or more control units 110. Each control unit provides the logic to operate and control one or more input/output devices and adapts, through the use of common facilities, the characteristics of each input/output device to the link interface provided by the channel. The common facilities provide for the execution of input/output operations, indications concerning the status of the input/output device and control unit, control of the timing of data transfer over the channel path and certain levels of input/output device control.
Each control unit 110 is attached via a connection 126 (e.g., a bus) to one or more input/output devices 112. Input/output devices 112 receive information or store information in main memory 102 and/or other memory. Examples of input/output devices include card readers and punches, magnetic tape units, direct access storage devices, displays, keyboards, printers, pointing devices, teleprocessing devices, communication controllers and sensor based equipment, to name a few.
Input/output operations are initiated with device 112 by executing input/output instructions that designate the subchannel associated with the device. In one embodiment, input/output operations are initiated and controlled by, for instance, a START SUBCHANNEL instruction, which employs channel command words. The START SUBCHANNEL instruction is executed by central processing unit 104 and is part of the central processing unit program that supervises the flow of requests for input/output operations from other programs that manage or process the input/output data.
When a START SUBCHANNEL instruction is executed, parameters are passed to the target subchannel requesting that channel subsystem 108 perform a start function with the input/output device associated with the subchannel. The channel subsystem performs the start function by using information at the subchannel, including the information passed during the execution of the START SUBCHANNEL instruction, to find an accessible channel path to the device. Once a device is selected, execution of an input/output operation is accomplished by the decoding and executing of a channel command word by channel subsystem 108 and input/output device 112. The channel command word specifies the command to be executed, and one or more channel command words arranged for sequential execution form a channel program. Both instructions and channel command words are fetched from main memory 102, as one example.
The START SUBCHANNEL instruction, as well as channels, control units and channel command words are described in detail in “IBM®z/Architecture Principles of Operation,” Publication No. SA22-7832-04, 5th Edition, September 2005, which is hereby incorporated herein by reference in its entirety. One or more of these components are also described in U.S. Pat. No. 5,461,721 entitled “System For Transferring Data Between I/O Devices And Main Or Expanded Storage Under Dynamic Control Of Independent Indirect Address Words (IDAWS),” Cormier et al., issued Oct. 24, 1995, and U.S. Pat. No. 5,526,484 entitled “Method And System For Pipelining The Processing Of Channel Command Words,” Casper et al., issued Jun. 11, 1996, each of which is hereby incorporated herein by reference in its entirety. IBM is a registered trademark of International Business Machines Corporation, Armonk, N.Y., USA. Other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies.
Further details related to processing an I/O request to transfer data are described with reference to
In response to executing the START SUBCHANNEL instruction, execution of the channel program commences. In particular, the first CCW of the program is processed. The CCW has a number of fields that control processing. These fields include, for instance, a command code 210 that specifies the operation to be performed; a plurality of flags 212 used to control the I/O operation; for commands that specify the transfer of data, a count field 214 that specifies the number of bytes in the storage area designated by the CCW to be transferred; and a data address 216 that points to a location in main memory that includes data, when indirect addressing is not employed, or in this case, when modified indirect data addressing is employed, to a list (e.g., contiguous list) of modified indirect data address words (MIDAWs) to be processed.
There are various I/O operations that can be performed, including, but not limited to, write, read, read backward, control and sense operations. With the write, read, control and sense operations, memory locations are used in ascending order of addresses. As information is transferred to or from memory, the address from the address field is incremented, and the count from the count field is decremented. The read backward operation places data in memory in a descending order of addresses, and both the count and the address are decremented. When the count reaches zero, the memory area defined by the CCW is exhausted.
In accordance with an aspect of the present invention, modified indirect data addressing (MIDA) is employed. MIDA permits a single channel command word to control the transfer of up to, for instance, 65,535 bytes of data that span noncontiguous blocks in main memory (or other memory, in another embodiment). Each block of memory to be transferred may be specified on any boundary and be of any length. Modified indirect data addressing is controlled by a flag in the ORB and specified by a flag in the CCW which, when both are set, indicate that the CCW data address is not used to directly address data, but instead, points to a contiguous list of one or more modified indirect data address words (MIDAWs). The number of MIDAWs in the list depends on the count in the CCW in that the total of all MIDAW counts is to equal the CCW count. There are to be enough MIDAWs to transfer the amount of data specified in the CCW count field.
Each MIDAW 220 is created by an operating system or device driver, as examples, and has a plurality of fields, including, for instance:
When modified indirect data addressing is specified, the data address field of the CCW designates the location of the first MIDAW to be used for data transfer for the CCW command. Additional MIDAWs, if needed for completing the data transfer for the CCW, are fetched from successive locations in memory. The number of MIDAWs used for a CCW is determined by the count field of the CCW in relation to the count fields in the list of MIDAWs designated by the CCW.
The total number of bytes that can be transferred or skipped or both by a single MIDAW list is limited by the CCW count field. The sum of the count fields in all of the MIDAWs in the list designated by the CCW should equal the value in the count field of the CCW.
The MIDAW designated by the CCW can designate any location within memory. When the MIDAW skip flag is zero and the CCW specifies a read, write, control, sense ID, or sense command, data is transferred to or from successively higher memory locations until the number of bytes specified by the MIDAW count field have been transferred. When the MIDAW skip flag is zero and the CCW specifies a read backwards command, data is transferred to successively lower memory locations until the number of bytes specified by the MIDAW count field have been transferred. When the MIDAW skip flag is one and CCW specifies a read, control, sense ID, or sense command, skipping occurs to successively higher memory locations until the number of bytes specified by the MIDAW count field have been skipped. When the MIDAW skip flag is one and the CCW specifies a read backwards command, skipping occurs to successively lower memory locations until the number of bytes specified by the MIDAW count field have been skipped.
When the specified number of bytes have been transferred or skipped and a subsequent MIDAW is specified, the control of data transfer is then passed to the next MIDAW in the list. Like the MIDAW designated by the CCW, subsequent MIDAWs may designate any location and any length.
Although one MIDAW and one CCW are depicted in
MIDAWs pertaining to the current CCW or a prefetched (fetched in advance of use) CCW may be prefetched. The number of MIDAWs that can be prefetched is not to exceed that required to satisfy the count in the CCW that designates the MIDAWs, in one embodiment. Any MIDAWs that are prefetched for a CCW and do not receive control over the I/O operation are not used. The action of transferring control from one MIDAW to the next is transparent to any attached device. A MIDAW takes control of data transfer when the operative CCW takes control (for the first MIDAW in a list) or when the last byte specified by the previous MIDAW has been transferred (for all subsequent MIDAWs in a list) and the operative CCW specifies the transfer of additional data.
A MIDAW does not take control of an I/O operation, if the count in the CCW has reached zero with the transfer of the last byte of data for the previous MIDAW. Program or access errors detected in prefetched MIDAWs are not indicated to the program until the MIDAW takes control of data transfer, even if an attempt had been made to prefetch that data.
Further details regarding processing a MIDAW are described with reference to
Returning to INQUIRY 310, if there is no more data to be transferred for this CCW, a further inquiry is made as to whether there is another MIDAW to be processed, INQUIRY 315. If so, a mismatch is indicated, indicating that there are more MIDAWs than there is data to be transferred, STEP 316. However, if there is not another MIDAW to be processed (or, in another embodiment, after specifying error 314 and/or error 316), a determination is made as to whether there are more CCWs to be processed, INQUIRY 318. In one example, this is determined by a flag in the current CCW. Should there be more CCWs to be executed, processing continues with STEP 304. Otherwise, processing of the channel program is complete.
Described in detail above is a technique that provides flexible control of transferring data between, for instance, I/O devices and noncontiguous memory, under control of modified indirect data address words. Modified indirect data addressing provides a more flexible and more usable technique for transferring data between a device and multiple noncontiguous blocks of memory. It permits a single CCW to control the transfer of data beginning and ending on any boundary (i.e., non-page boundaries) between a device and memory mapped to pages in a virtual address space. MIDA also permits the transfer of larger than noncontiguous 4 KB blocks of data.
One or more aspects of the present invention can be included in an article of manufacture (e.g., one or more computer program products and/or systems) having, for instance, computer usable media. The media have therein, for instance, computer readable program code means of logic (e.g., instructions, code, commands, etc.) to provide and facilitate the capabilities of the present invention. The article of manufacture can be included as a part of a computer system or sold separately.
One example of an article of manufacture or a computer program product incorporating one or more aspects of the present invention is described with reference to
A sequence of program instructions or a logical assembly of one or more interrelated modules defined by one or more computer readable program code means or logic direct the performance of one or more aspects of the present invention.
Advantageously, a scatter/gather technique for transferring data is provided. A capability of transferring data is provided in which the amount of data to be transferred is independent of a specific memory boundary. This technique provides relief to the program selectable maximum 2 KB/4 KB block size limitation imposed by other indirect data addressing techniques. Further, a separate transfer count is associated with each indirect data address, and control is transferred from one listed indirect data address to the next based on the count field associated with the indirect data address. Skipping on a per indirect address and associated count basis is also enabled and validation of the size of the list of indirect data addresses is provided.
Advantageously, discontiguous blocks of memory may be specified on any boundary and length (e.g., in one embodiment, up to 64 K-1) without using chained data CCWs.
Modified indirect data addressing provides a mechanism in which a program can specify a channel program that controls the transfer of data that spans noncontiguous blocks of memory that are on any boundary and of any size. Such a channel program includes, for instance, one or more channel command words whose address field is not used to address data, but is used to designate the address of a contiguous list of modified indirect data address words. The list of MIDAWs is not a list of addresses, but a list of control blocks, in which each control block (i.e., MIDAW) includes information used in processing.
Each MIDAW includes a count field that specifies the amount of data to be transferred when that MIDAW is in control. The transfer of control from one MIDAW on the list to the next is controlled by a combination of the CCW count field and the MIDAW count field. When data transfer begins, the first MIDAW on the list is used to designate where, for instance, in main memory the transfers begins. If the value of the CCW count field exceeds the value of the count field in the first MIDAW and the last MIDAW flag is zero, the next MIDAW assumes control and data transfer continues at the main memory address designated by that MIDAW. This process of passing control to successive MIDAWs in the list continues until a total amount of data specified by the CCW count field has been transferred.
Because the MIDAW includes an address field and a count field, the memory location specified by any MIDAW can begin and end on any boundary.
Further, each MIDAW includes a flag field in which there is a skip indicator. If the skip indicator is one when the MIDAW gets control during data transfer, the range of memory specified by the MIDAW is skipped and no data transfer is performed for that range.
The MIDAW flag field also includes an indicator that the MIDAW is the last MIDAW in the list. Thus, if the CCW count field specifies the transfer of control to a subsequent MIDAW when this indicator is one, there is a mismatch between CCW and the MIDAW list. Similarly, if the total amount of data specified by the CCW has been transferred and the MIDAW currently in control has its flag set to zero, there is also a mismatch between the CCW and MIDAW list. In either case, the program can be informed via a channel program check to indicate the error.
Although various embodiments are described above, these are only examples. Processing environments other than those described herein, including others that use I/O subsystems, other than channel subsystems, can incorporate and use one or more aspects of the present invention. Further, although various control blocks have been shown, the location of the information within those control blocks may be other than shown herein. Further, each control block may include additional, less or different information than described herein. For instance, there may be additional, fewer and/or different fields, including fields that may include additional, fewer and/or different flags. Further, there may be additional, fewer and/or different field sizes. Yet further, although main memory is mentioned or described in various portions of the embodiment, one or more aspects of the present invention may be applicable to other memory.
In yet further embodiments, it is possible to implement certain restrictions, if desired. For example, a restriction may be implemented that a MIDAW list may not be specified to cross a particular boundary, such as a 4 KB byte boundary. This would limit the maximum MIDAW list size to 256 MIDAWs. Further, a single MIDAW may specify a data count that may not exceed a particular boundary, such as a 4 KB boundary, and/or is not to specify the transfer of data across a 4 KB byte boundary. In yet further examples, the skip flag need not only apply to read operations. Any other changes and/or enhancements may be made without departing from the spirit of the present invention.
Moreover, an environment may include an emulator (e.g., software or other emulation mechanisms), in which a particular architecture or subset thereof is emulated. In such an environment, one or more emulation functions of the emulator can implement one or more aspects of the present invention, even though a computer executing the emulator may have a different architecture than the capabilities being emulated. As one example, in emulation mode, the specific instruction or operation being emulated is decoded, and an appropriate emulation function is built to implement the individual instruction or operation.
In an emulation environment, a host computer includes, for instance, a memory to store instructions and data; an instruction fetch unit to fetch instructions from memory and to optionally, provide local buffering for the fetched instruction; an instruction decode unit to receive the instruction fetch unit and to determine the type of instructions that have been fetched; and an instruction execution unit to execute the instructions. Execution may include loading data into a register for memory; storing data back to memory from a register; or performing some type of arithmetic or logical operation, as determined by the decode unit. In one example, each unit is implemented in software. For instance, the operations being performed by the units are implemented as one or more subroutines within emulator software.
Further, a data processing system suitable for storing and/or executing program code is usable that includes at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements include, for instance, local memory employed during actual execution of the program code, bulk storage, and cache memory which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution.
Input/Output or I/O devices (including, but not limited to, keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening I/O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems, and Ethernet cards are just a few of the available types of network adapters.
The capabilities of one or more aspects of the present invention can be implemented in software, firmware, hardware, or some combination thereof. At least one program storage device readable by a machine embodying at least one program of instructions executable by the machine to perform the capabilities of the present invention can be provided.
The flow diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted, or modified. All of these variations are considered a part of the claimed invention.
Although preferred embodiments have been depicted and described in detail there, it will be apparent to those skilled in the relevant art that various modifications, additions, substitutions and the like can be made without departing from the spirit of the invention and these are therefore considered to be within the scope of the invention as defined in the following claims.
