Patent Application
20160154743
Cache memory may be utilized by storage controllers to reduce the number of input and output transactions to and from a storage unit. Cache memory may be arranged in accordance with logical block addressing (“LBA”) such that blocks of data therein are linearly or sequentially addressed. The blocks of data may be divided into multiple cache lines.
As noted above, linearly addressed cache memory blocks may be divided into multiple cache lines. Each cache line may have bits of metadata associated therewith that indicates whether a block of data in the cache line contains valid data (“valid bit”) or whether a block of data contains dirty data (“dirty bit”). In one example, dirty data may be defined as a block of data that has been altered since it was cached from storage such that the block of data in cache is more recent than its corresponding block in storage. A cache placement module may be used to determine which data blocks should be written to storage from cache memory to make room for new data. Such modules may search for a cache line without dirty data and may overwrite the blocks therein with the new data.
If a cache placement module is unable to locate a cache line free of dirty data, a storage controller may need to “flush” dirty data from a cache line before it can overwrite it with new data, In one example, a flush transaction may be defined as a write of dirty data back to storage from cache memory. Unfortunately, these flush transactions may hinder the overall performance of a storage unit. The performance of the storage unit may depend on how fast the controller can flush dirty data from cache memory. A heavy workload may cause a considerable increase in read/write transactions executed in storage. In turn, the deterioration in performance caused by the increase in transactions may be problematic for applications writing and reading data to and from storage.
In view of the foregoing, disclosed herein are a system, non-transitory computer readable medium, and method for reducing input and output transactions. In one example, it is determined whether a first set of dirty data blocks, a second set of dirty data blocks, and a number of data blocks therebetween can be flushed with one transaction in order to reduce overall input and output transactions to and from a storage unit. Rather than confining the flush transaction to dirty data scheduled for replacement by new cache data, the techniques disclosed herein may determine whether it's feasible to flush additional dirty data in the same transaction. Thus, the system, non-transitory computer readable medium, and method disclosed herein may enhance the performance of a storage system by further reducing the overall number of input and output transactions to and from the storage unit. The aspects, features and advantages of the present disclosure will be appreciated when considered with reference to the following description of examples and accompanying figures. The following description does not limit the application; rather, the scope of the disclosure is defined by the appended claims and equivalents.
Non-transitory computer readable media may comprise any one of many physical media such as, for example, electronic, magnetic, optical, electromagnetic, or semiconductor media. More specific examples of suitable non-transitory computer-readable media include, but are not limited to, a portable magnetic computer diskette such as floppy diskettes or hard drives, a read-only memory (“ROM”), an erasable programmable read-only memory, a portable compact disc or other storage devices that may be coupled to computer apparatus 100 directly or indirectly. Alternatively, non-transitory CRM 112 may be a random access memory (“RAM”) device or may be divided into multiple memory segments organized as dual in-line memory modules (“DIMMs”). The non-transitory CRM 112 may also include any combination of one or more of the foregoing and/or other devices as well. While only one processor and one non-transitory CRM are shown in
The instructions residing in controller 114 may comprise any set of instructions to be executed directly (such as machine code) or indirectly (such as scripts) by processor 110. In this regard, the terms “instructions,” “scripts,” and “applications” may be used interchangeably herein. The computer executable instructions may be stored in any computer language or format, such as in object code or modules of source code. Furthermore, it is understood that the instructions may be implemented in the form of hardware, software, or a combination of hardware and software and that the examples herein are merely illustrative.
In another example, controller 114 may be firmware executing in a controller for storage unit 116. While
As noted above, a cache memory may be utilized to cache data from the storage unit. In one example, controller 114 may instruct processor 110 to read a request to write a first set of dirty data blocks back to storage unit 116 from the cache memory. This request may originate from a cache placement module. In another example, controller 114 may instruct processor 110 to determine whether the first set of dirty data blocks, a second set of dirty data blocks, and a number of data blocks therebetween can be written to storage unit 116 from cache memory with one flush transaction. This may reduce overall input and output transactions to and from storage unit 116. In a further example, in order to determine whether one transaction may be used in such a way, controller 114 may determine whether the number of data blocks between the first and second set of dirty data blocks is within a predetermined threshold. In another example, controller 114 may determine whether there is sufficient bandwidth to carry out the transaction. In yet another aspect, controller 114 may determine whether each data block between the first and second set of dirty data blocks is valid. If nor, valid data may be read from storage into any data block between the first and second set that contains invalid data. In one example, invalid data may be defined as data that has not been cached from storage.
Working examples of the system, method, and non-transitory computer readable medium are shown in
As shown in block 202 of
Referring back to
Since intermediate data blocks 313 are non-dirty, the data in these intermediate blocks may already be synchronized with their corresponding blocks in storage. While including these intermediate, non-dirty data blocks in the flush transaction may be redundant, if the non-dirty data blocks are outnumbered by the dirty data blocks of the first and second set combined, the benefit of including these non-dirty blocks in the one flush transaction may outweigh the cost of having extra flush transactions in the future. Conversely, if the dirty data blocks in the first and second set combined are outnumbered by the non-dirty data blocks therebetween, the cost may outweigh the benefit.
Other factors that may be considered when determining whether to use one transaction In flush discontinuous dirty data blocks may be whether the system has enough bandwidth to execute the one transaction. In another example, it may be determined whether each data block between the two sets of dirty data blocks contains valid data. This may be determined by checking the valid bit associated with each data block. If a data block between the first and second set of dirty data blocks contains invalid data, valid data may be read into the data block. As noted above, invalid data may be defined as data that was not cached from storage. If the flush transaction were executed with such invalid data between the first and second set, the data blocks in storage corresponding to the invalid data blocks may be overwritten. Therefore, the invalid data in the blocks between the first and second set of dirty data blocks may be replaced with valid data from storage before executing the one flush transaction. In this instance, in addition to writing the first and second set of dirty data blocks, the one flush transaction also rewrites the valid data just read into the invalid data blocks right back to storage. In one example, the cost of reading valid data from storage into the invalid data blocks is outweighed by the benefits of reduced future transactions, when the number of non-dirty data blocks is within the predetermined threshold as explained above.
Referring now to
Advantageously, the foregoing system, method, and non-transitory computer readable medium reduces overall input and output transactions to and from storage. Rather than limiting a flush transaction to dirty data that will be replaced with new data, additional dirty data may also be flushed in the same transaction. Thus, the techniques disclosed herein may cope with heavier workloads better than conventional systems. In turn, the performance of user applications may be maintained despite increased stress on the storage unit.
Although the disclosure herein has been described with reference to particular examples, it is to be understood that these examples are merely illustrative of the principles of the disclosure. It is therefore to be understood that numerous modifications may be made to the examples and that other arrangements may be devised without departing from the spirit and scope of the disclosure as defined by the appended claims. Furthermore, while particular processes are shown in a specific order in the appended drawings, such processes are not limited to any particular order unless such order is expressly set forth herein; rather, processes may be performed in a different order or concurrently and steps may be added or omitted.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2013/047536 | 6/25/2013 | WO | 00 |
