Patent Application
20230120513
Edge connectors are widely used for add-in cards (AICs) in high-speed differential I/O (input/output) applications. For example, most desktop computers include multiple PCIe (Peripheral Component Interconnect Express) expansion slots with connectors mounted to the motherboard that are configured to interface with edge connectors on PCIe AICs (also referred to as expansions cards). This PCIe connectors are mounted perpendicular to the motherboard PCB (printed circuit board). Edge connectors of various configurations are also used to connect memory modules, such as DDR (Double Data Rate) DRAM Dual Inline Memory Modules (DIMMs) and Small Outline Dual Inline Memory Modules (SO DIMMs).
Laptop and notebook computers have limited space for AICs and DIMMs. To address this, PCI-SIG (Special Interest Group), the PCIe standards body, developed and standardized the PCIe M.2 card edge (commonly referred to a M dot 2) and mating PCIe M.2 connector, which is a right-angle connector that enables the AIC to be installed parallel to the motherboard. Examples of an M.2 edge card 100 and an M.2 connector 120 are shown in
M.2 edge card 100 includes a PCB 102 including an PCIe M.2 edge connector 104. Various integrated circuits (aka chips) and other electronic components are mounted to PCB 102, including a memory controller chip 106, a DRAM memory chip 108, and a pair of nonvolatile (NV) memory chips 110 and 112. PCIe M.2 edge connector has a Key B+M form factor with pins on a single side (the top side of SSD edge card 100 in this example).
PCIe M.2 connector 120 includes a body 122 having a slot in which edge contacts 124 are disposed. The edge contacts 124 are electrically coupled to contacts 126, which are soldered to pads in the motherboard PCB (or other type of PCB). When installed in PCIe M.2 connector 120, the pins in PCIe M.2 edge connector are electrically coupled to edge contacts 124, and thus to the pads in the PCB.
The PCIe M.2 connector was designed for PCIe3 and PCI4 (3rd and 4th generation) standards. For high speed I/O, such as PCIe5 (PCIe 5th generation), the M.2 connector shows performance degradation. The connector performance improvement is critical for higher data rate I/O applications. In addition, the pin count of this connector is not scalable with given PCIe edge card form factor, which limit the bandwidth of the card. Similarly, SODIMMs and their associated edge connectors were not designed to meet the performance criteria for the current and future generations of DDR DRAM.
Recently, DDR DRAM memory packaging solutions employing Compression Attached Memory Module (CAMM) technology have been introduced. While CAMM has the performance and upgradability advantages, it has its trade-off of potentially impeding the system miniaturization effort. For example, the size of CAMM modules tend to increase proportionally with the amount of memory installed on the modules (for a given DDR DRAM generation and DRAM package).
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified:
Embodiments of foldable Compression Attached Memory Modules (fCAMMs) and associated apparatus, assemblies and systems are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
For clarity, individual components in the Figures herein may also be referred to by their labels in the Figures, rather than by a particular reference number. Additionally, reference numbers referring to a particular type of component (as opposed to a particular component) may be shown with a reference number followed by “(typ)” meaning “typical.” It will be understood that the configuration of these components will be typical of similar components that may exist but are not shown in the drawing Figures for simplicity and clarity or otherwise similar components that are not labeled with separate reference numbers. Conversely, “(typ)” is not to be construed as meaning the component, element, etc. is typically used for its disclosed function, implement, purpose, etc. Also, in the Figures herein components that share the same reference numbers in multiple figures refer to the same component or a similar component when the Figures illustrate different embodiments, such as different systems, assemblies, etc.
fCAMM 202 includes a compression contact module 214 coupled to first and second fold modules 216 and 218 via first and second flexible interconnects 219 and 220. Fold module 216 includes a PCB 222 to which a plurality of DRAM devices 224 are mounted, while fold module 218 includes a PCB 226 to which a plurality of DRAM devices 224 are likewise mounted.
A CMT (contact mount technology) connector 228 is disposed between compression contact module 214 and motherboard 204. CMT connector 228 includes an array of spring-loaded CMT contacts 230 (which may also be referred to as CMT pins) that are respectively coupled to CMT contact pads in a first array of CMT contact pads 232 disposed on the underside of compression contact module 214 and a second array of CMT contact pads 234 disposed on the top surface of motherboard 204.
Under the orientation shown in
To effect the downward compression force a pair of upper and lower bolster plates 236 and 238 are used. Lower bolster plate 238 is disposed on the bottom surface of motherboard 204, while upper bolster plate 236 is disposed above PCBs 222 and 226. In the illustrated embodiment, a pair of internally threaded standoffs 240 (one is shown in this view) are coupled to lower bolster plate 238 (e.g., integrally manufactured such that the lower bolster plate and the two internally threaded standoff are a single piece). A pair of screws 242 are threaded into the threaded portion of internally threaded standoffs 240. In another embodiment, a bolt is used that is either threaded into a threaded insert in lower bolster plate 238 (e.g., a KEENSERT™ or the like), or the bolt is threaded into a nut disposed below lower bolster plate 238.
Generally, “wiring” in the motherboard PCB and the PCBs (or substrates) used for compression contact module 214 and fold modules 216 and 218 is used to interconnect “pins” on CPU/SoC package 206 (in this illustrated example solder balls 212) to “pins” on DRAM devices 224. Generally, DRAM devices 224 comprise a DRAM package or “chip” with some means for coupling signals from the DRAM die to the PCB to which the DRAM device is mounted. For example, DRAM devices may employ BGAs in some embodiments, or may employ an array of BGA pads with the BGA solder balls formed on the PCB. The “wiring” generally comprises via and circuit traces formed in various layers in the PCBs, as illustrated by a routing trace 244. Similar routing traces would be used in the PCB/substrate for compression contact module 214 to couple CMT contact pads 232 to first ends of flexible interconnects 219 and 220 and routing traces in PCBs 222 and 226 would be used to the couple second ends of flexible interconnects 219 and 220 to “pins” on DRAM devices 224.
As further shown in
As shown in
In addition to routing traces coupling pins on CPU/SoC/XPU 210 to CMT contact pads 234, portions of the CMT contact pads will be coupled to a ground plane and one or more voltage lines provided by a power supply and voltage regulation module (VRM) 270. Generally, the power supply may be mounted to the motherboard or be separate and provide voltage input(s) to one or more VRMs. The one or more VRMs provide output voltages that are coupled to groups of CMT contact pads 234 that are used to provide input power to various circuitry in fCAMM 202.
Generally, the PCBs described and illustrated herein may employ known PCB structures. For example, such PCBs may be organic or ceramic-based PCBs.
In addition to using an interposed CMT connector, such as CMT connector 228, other means may be used to couple signals from a motherboard to a compression contact module. For example, in the embodiment of a system 300 illustrated in
As shown in the detailed views of
As shown in
fCAMM 402 includes a compression contact module 414 coupled to first and second fold modules 416 and 418 via first and second flexible interconnects 419 and 420. Fold module 416 includes a PCB 422 to which two columns of DRAM devices 424 are mounted, while fold module 418 includes a PCB 426 to which two columns of DRAM devices 424 are likewise mounted.
A CMT connector 428 is disposed between compression contact module 414 and motherboard 404. CMT connector 428 includes an array of spring-loaded CMT contacts 430 that are respectively coupled to CMT contact pads in a first array of CMT contact pads 432 disposed on the underside of compression contact module 414 and a second array of CMT contact pads 434 disposed on the top surface of motherboard 404.
System 400 includes an upper bolster plate 445, a compression contact module bolster plate 436, and a lower bolster plate 438 to which a pair of externally threaded standoffs 440 are coupled (e.g., integrally coupled to form a single piece in one embodiment). Other components (for each of externally threaded standoffs 440) include a lower nut 444, a spacer 446, and an upper nut 449. As an option, a pair of bolts with a sufficient thread length may be used in place of a threaded standoffs, noting in this instance the bolts would be inserted through clearance holes in the lower bolster plate rather than be a single piece.
As further shown in
In an aspect, compression contact module 414 may include a first width, PCB 422 may include a second width and PCB 426 may include a third width. In an aspect shown in
Alternatively, the first width may be configured to be equivalent or larger than the respective second and third widths, for example, to accommodate increased number of arrays 436 of CMT contact pads 432 for improved functionality; respective L1/L2 may be further reduced accordingly.
During assemble, the externally threaded standoffs are passed through a pair of clearance holes 462 in motherboard 404, which has a plan view configuration similar to motherboard 204 shown in
Next, fold module 418 is installed by flipping the fold module over such that the DRAM devices 424 are on the underside of PCB 426. During installation, the upper portion of externally threaded standoffs 440 pass through clearance holes 460 and 461. Spacers 446 are then slipped over the upper portion of externally threaded standoffs 440. Fold module 416 is then installed by flipping the fold module over such that the DRAM devices 424 are on the underside of PCB 422 with the upper portion of externally threaded standoffs 440 passing through clearance holes 456 and 458 in PCB 422. At this point, upper bolster plate 445 is installed over PCB 422 and upper nut 449 is threaded onto the top portions of externally threaded standoffs 440 until the assembled components are held securely in place.
As with the embodiment shown in
As further shown in
Compute platform 600 includes a processor 610, which provides processing, operation management, and execution of instructions for compute platform 600. Processor 610 can include any type of microprocessor, CPU, graphics processing unit (GPU), processing core, or other processing hardware to provide processing for compute platform 600, or a combination of processors. Processor 610 may also comprise an SoC or XPU. Processor 610 controls the overall operation of compute platform 600, and can be or include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices.
In one example, compute platform 600 includes interface 612 coupled to processor 610, which can represent a higher speed interface or a high throughput interface for system components that needs higher bandwidth connections, such as memory subsystem 620 or graphics interface components 640. Interface 612 represents an interface circuit, which can be a standalone component or integrated onto a processor die. Where present, graphics interface 640 interfaces to graphics components for providing a visual display to a user of compute platform 600. In one example, graphics interface 640 can drive a high definition (HD) display that provides an output to a user. High definition can refer to a display having a pixel density of approximately 100 PPI (pixels per inch) or greater and can include formats such as full HD (e.g., 1080p), retina displays, 4K (ultra-high definition or UHD), or others. In one example, the display can include a touchscreen display. In one example, graphics interface 640 generates a display based on data stored in memory 630 or based on operations executed by processor 610 or both.
Memory subsystem 620 represents the main memory of compute platform 600 and provides storage for code to be executed by processor 610, or data values to be used in executing a routine. Memory 630 of memory subsystem 620 may include one or more memory devices such as DRAM devices, read-only memory (ROM), flash memory, or other memory devices, or a combination of such devices. Memory 630 stores and hosts, among other things, operating system (OS) 632 to provide a software platform for execution of instructions in compute platform 600. Additionally, applications 634 can execute on the software platform of OS 632 from memory 630. Applications 634 represent programs that have their own operational logic to perform execution of one or more functions. Processes 636 represent agents or routines that provide auxiliary functions to OS 632 or one or more applications 634 or a combination. OS 632, applications 634, and processes 636 provide software logic to provide functions for compute platform 600. In one example, memory subsystem 620 includes memory controller 622, which is a memory controller to generate and issue commands to memory 630. It will be understood that memory controller 622 could be a physical part of processor 610 or a physical part of interface 612. For example, memory controller 622 can be an integrated memory controller, integrated onto a circuit with processor 610.
While not specifically illustrated, it will be understood that compute platform 600 can include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, interface buses, or others. Buses or other signal lines can communicatively or electrically couple components together, or both communicatively and electrically couple the components. Buses can include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuitry or a combination. Buses can include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) standard 1394 bus.
In one example, compute platform 600 includes interface 614, which can be coupled to interface 612. Interface 614 can be a lower speed interface than interface 612. In one example, interface 614 represents an interface circuit, which can include standalone components and integrated circuitry. In one example, multiple user interface components or peripheral components, or both, couple to interface 614. Network interface 650 provides compute platform 600 the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 650 can include an Ethernet adapter, wireless interconnection components, cellular network interconnection components, USB (universal serial bus), or other wired or wireless standards-based or proprietary interfaces. Network interface 650 can exchange data with a remote device, which can include sending data stored in memory or receiving data to be stored in memory.
In one example, compute platform 600 includes one or more I/O interface(s) 660. I/O interface(s) 660 can include one or more interface components through which a user interacts with compute platform 600 (e.g., audio, alphanumeric, tactile/touch, or other interfacing). Peripheral interface 670 can include any hardware interface not specifically mentioned above. Peripherals refer generally to devices that connect dependently to compute platform 600. A dependent connection is one where compute platform 600 provides the software platform or hardware platform or both on which operation executes, and with which a user interacts.
In one example, compute platform 600 includes storage subsystem 680 to store data in a nonvolatile manner. In one example, in certain system implementations, at least certain components of storage subsystem 680 can overlap with components of memory subsystem 620. Storage subsystem 680 includes storage device(s) 684, which can be or include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic, solid state, or optical based disks, or a combination. Storage device(s) 684 holds code or instructions and data 686 in a persistent state (i.e., the value is retained despite interruption of power to compute platform 600). A portion of the code or instructions may comprise platform firmware that is executed on processor 610. Storage device(s) 684 can be generically considered to be a “memory,” although memory 630 is typically the executing or operating memory to provide instructions to processor 610. Whereas storage device(s) 684 is nonvolatile, memory 630 can include volatile memory (i.e., the value or state of the data is indeterminate if power is interrupted to compute platform 600). In one example, storage subsystem 680 includes controller 682 to interface with storage device(s) 684. In one example controller 682 is a physical part of interface 614 or processor 610 or can include circuits or logic in both processor 610 and interface 614. In one example, a storage device 684 may comprise an AIC such as an NVMe SSD that is mounted to the motherboard using a CMT connector using the assemble architecture shows in the Figures herein and discussed above.
Compute platform 600 may include an optional Baseboard Management Controller (BMC) 690 that is configured to effect the operations and logic corresponding to the flowcharts disclosed herein. BMC 690 may include a microcontroller or other type of processing element such as a processor core, engine or micro-engine, that is used to execute instructions to effect functionality performed by the BMC. Optionally, another management component (standalone or comprising embedded logic that is part of another component) may be used.
Power source 602 provides power to the components of compute platform 600. More specifically, power source 602 typically interfaces to one or multiple power supplies 604 in compute platform 600 to provide power to the components of compute platform 600. In one example, power supply 604 includes an AC to DC (alternating current to direct current) adapter to plug into a wall outlet. Such AC power can be renewable energy (e.g., solar power) power source 602. In one example, power source 602 includes a DC power source, such as an external AC to DC converter. In one example, power source 602 can include an internal battery or fuel cell source.
Various types of memory may be used in the fCAMMs described and illustrated herein, including standardized memory devices (e.g., chips and/or packages). Such standards include DDR4 (Double Data Rate version 4, initial specification published in September 2012 by JEDEC (Joint Electronic Device Engineering Council). DDR4E (DDR version 4), LPDDR3 (Low Power DDR version 3, JESD209-3B, August 2013 by JEDEC), LPDDR4 (LPDDR version 4, JESD209-4, originally published by JEDEC in August 2014), WIO2 (Wide Input/Output version 2, JESD229-2 originally published by JEDEC in August 2014, HBM (High Bandwidth Memory, JESD325, originally published by JEDEC in October 2013), DDR5 (DDR version 5, JESD79-5A, published October, 2021), DDR version 6 (currently under draft development), LPDDR5, HBM2E, HBM3, and HBM-PIM, or others or combinations of memory technologies, and technologies based on derivatives or extensions of such specifications. The specification for LPDDR6 is currently under development. The JEDEC standards are available at www.jedec.org.
As discussed above, in some embodiment the processors illustrated herein may comprise Other Processing Units (collectively termed XPUs). Examples of XPUs include one or more of Graphic Processor Units (GPUs) or General Purpose GPUs (GP-GPUs), Tensor Processing Units (TPUs), Data Processing Units (DPUs), Infrastructure Processing Units (IPUs), Artificial Intelligence (AI) processors or AI inference units and/or other accelerators, FPGAs and/or other programmable logic (used for compute purposes), etc. While some of the diagrams herein show the use of CPUs, this is merely exemplary and non-limiting. Generally, any type of XPU may be used in place of a CPU in the illustrated embodiments. Moreover, as used in the following claims, the term “processor” is used to generically cover CPUs and various forms of XPUs.
In the foregoing embodiments, the configuration of the arrays used for the CMT connectors and LGAs are exemplary and non-limiting. The number of contacts or pins may be greater than that shown, and the configuration and pitch of the arrays may vary to meet the system requirements. For example, in the case of the system 400, the doubling of DRAM devices relative to system 200 would generally result in the use of more Input/Output (I/O) signals and thus the need for more contacts or pins in the CMT connector and LGA assembly.
It is further noted that the LGA assembly components illustrated in
The fCAMM and associated assemblies and systems described and illustrated herein provide advantages over current CAMM solutions, including system miniaturization. For example, foldable CAMMs ensure the memory module X and Y dimensions do not grow exponentially with every increment of DRAM density. The increased area would have potentially caused components at the CPU core area, such as bulk power delivery (PD) components (inductors, capacitors), cooling fans, storage and radio M.2 modules to move further out, thus increasing the system footprint. The memory module board layer count may also be reduced, as an fCAMM includes multiple fold modules.
The fCAMM embodiments also provide enhanced signal integrity performance. For instance, they provide reduced signal latency between CPU, SoC, or XPU (e.g., processor) and DRAM memory devices through shorter and less distorted signal transmission path, e.g., direct signal interconnect paths between the processor and the multiple memory devices on both sides of the CAMM connector via the flexible interconnects for reduced signal crosstalk coupling and/or insertion loss.
Although some embodiments have been described in reference to particular implementations, other implementations are possible according to some embodiments. Additionally, the arrangement and/or order of elements or other features illustrated in the drawings and/or described herein need not be arranged in the particular way illustrated and described. Many other arrangements are possible according to some embodiments.
In each system shown in a figure, the elements in some cases may each have a same reference number or a different reference number to suggest that the elements represented could be different and/or similar. However, an element may be flexible enough to have different implementations and work with some or all of the systems shown or described herein. The various elements shown in the figures may be the same or different. Which one is referred to as a first element and which is called a second element is arbitrary.
In the description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. Additionally, “communicatively coupled” means that two or more elements that may or may not be in direct contact with each other, are enabled to communicate with each other. For example, if component A is connected to component B, which in turn is connected to component C, component A may be communicatively coupled to component C using component B as an intermediary component.
An embodiment is an implementation or example of the inventions. Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the inventions. The various appearances “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments.
Not all components, features, structures, characteristics, etc. described and illustrated herein need be included in a particular embodiment or embodiments. If the specification states a component, feature, structure, or characteristic “may”, “might”, “can” or “could” be included, for example, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the elements. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional elements.
As used herein, a list of items joined by the term “at least one of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C.
The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the drawings. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
