Patent Application
20250155493
The technology of the disclosure relates generally to memory devices and a method to force failure of a memory device prior to integrity testing.
Computing devices abound in modern society. The prevalence of these devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices enable enhanced user experiences. With the advent of the myriad functions available to such devices, the size and complexity of the operating systems used to control the computing devices have increased. Likewise, there is a general trend for increasingly large and complex software applications. This increase in size and complexity requires more available memory to support the host processor. In general, most of the memory is volatile random-access memory (RAM).
As the scope of functionality increases, the demands placed on the memory increase. More specifically, a computationally intense, lengthy process (e.g., high-end graphics rendering, machine learning, or artificial intelligence training) may be compromised if the memory is defective or fails while the process is being executed. In extreme cases, it only takes a few failed memory cells in the memory device to cause the process to be compromised. Accordingly, there are now companies that sell certification services that certify that a memory device meets a predefined threshold of viable cells (and/or provides a map to avoid the use of failed cells). For example, the ZEFR™ service made available by the assignee of the present disclosure is one such service. Finding all the cells that have failed and/or are likely to fail after installation provides room for innovation.
Aspects disclosed in the detailed description include systems and methods for forced early failure of cells within a memory device. In an exemplary aspect, a memory device such as a dynamic random-access memory (DRAM) chip is subjected to an elevated temperature and an electric field to cause unwanted particles within the chip to migrate rapidly into the circuit elements of a memory cell, thereby causing the memory cell to fail. Subsequent testing may identify this failed cell and verify that the remaining cells within the memory device are operational. By forcing the cell to fail prior to certification testing, the end user may be reasonably confident that the certification provided for the device will remain accurate for the lifetime of the device. In contrast, without this forced early failure, such unwanted particles may migrate after deployment and may cause cell failure while deployed, resulting in a botched operation.
In this regard, in one aspect, a method of forcing memory cell failure in a memory chip is disclosed. The method includes subjecting the memory chip having at least one memory cell to an elevated temperature for a predetermined amount of time sufficient to allow particles proximate or within the at least one memory cell to migrate to a vulnerable area.
In another aspect, a method of forcing memory cell failure in a memory chip is disclosed. The method includes applying an electrical field to the memory chip having at least one memory cell for sufficient time to allow particles proximate or within the memory cell to migrate to a vulnerable area.
In another aspect, a memory chip comprising a memory cell having a particle in a vulnerable area is disclosed, wherein the particle migrated to the vulnerable area after manufacturing as a result of the memory chip being exposed to an elevated temperature above 150 C and an electrical field.
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, no intervening elements are present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, no intervening elements are present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, no intervening elements are present.
Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
The terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Aspects disclosed in the detailed description include systems and methods for forced early failure of cells within a memory device. In an exemplary aspect, a memory device such as a dynamic random-access memory (DRAM) chip is subjected to an elevated temperature and an electric field to cause unwanted particles within the chip to migrate rapidly into the circuit elements of a memory cell, thereby causing the memory cell to fail. Subsequent testing may identify this failed cell and verify that the remaining cells within the memory device are operational. By forcing the cell to fail prior to certification testing, the end user may be reasonably confident that the certification provided for the device will remain accurate for the lifetime of the device. In contrast, without this forced early failure, such unwanted particles may migrate after deployment and may cause cell failure while deployed, resulting in a botched operation.
Before addressing aspects of the present disclosure, a discussion of memory devices and sources of contamination is provided so that the discussion of the present disclosure has context. A discussion of aspects of the present disclosure begins below with reference to
In this regard,
Within a generic memory chip 102, a memory cell 200 is positioned, as shown in
Regardless of the specific structure, during manufacturing, there may be extraneous material that adheres to or is inadvertently left on the memory cell 200. For example, during back grinding of the wafer (i.e., the substrate 202), copper particles 212A or 212B may remain on a surface of the substrate 202. When located outside the substrate 202, operation of the memory cell 200 may occur unimpeded. However, over time, the copper particles 212A, 212B may migrate into the substrate 202 and even into a doped section 204, 206. The presence of a copper particle 212A, 212B in the doped sections 204, 206 (and potentially even in the substrate 202) may change the operation of the memory cell 200 and result in the memory cell 200 being considered failed.
In general, there are thousands of memory cells 200 in a given memory chip 102. Thus, the failure of a given memory cell 200 does not specifically impact the overall utility of the memory chip 102. However, if the memory cell 200 fails while the memory chip 102 is in use (e.g., by a host processor (not shown)), and particularly if the memory cell 200 fails while a bit being used by an executing process is stored therein, such failure may interrupt or otherwise interfere with the executing process. Because such failure is a result of relatively slow migration (i.e., after the memory chip 102 has been in use for some time), a memory chip 102 may experience memory cell failure after that particular memory cell has been certified as valid. Failure of a certified memory cell reduces trust in the certification process as well as inconveniences the end user.
Accordingly, there is an interest in improving the ability to detect such potential future failures. Exemplary aspects of the present disclosure provide one such improvement by forcing premature failure of memory cells that are susceptible to such migration-based failures. In particular, aspects of the present disclosure accelerate the migration of such particles through the use of applied temperature and electric fields. When a memory chip 102 is subjected to such conditions, particles that may exist are more likely to migrate to a vulnerable portion of a memory cell 200 and cause a failure that can be detected by a certification process. As noted, the known failure of a given cell before deployment is readily handled compared to a cell that may fail during an executing process.
A process 300 for forced failure is set forth in
The memory chip 102 is then subjected to an electrical field 400 (block 306). The direction of the field may be based on the expected ionization of the particle and a desired direction of migration (e.g., a copper particle is likely a positive charge, and the desire is to move the particle into the doped sections, so a field that would move a positive ion in that direction is applied, with the understanding that there may be negatively charged particles and as such, aspects of the present disclosure contemplate using both positive and negative electrical fields to move the particles). As illustrated in
Remove heat and electrical field 400 after a predetermined amount of time (block 308). At this point, the particles 212A, 212B will have migrated to the vulnerable portions of the memory cell 200 (i.e., the doped sections 204, 206), as shown in
After the forced migration, the memory chip 102 may undergo certification testing (block 310) to see what memory cells 200 have failed. With this identification, a reliable memory device may be used by the end user.
It should be appreciated that the type of particle may be different. For example, the particle could be a bit of solder material from die attaching, a bit of mold compound, or the like. Likewise, the particles may not be on the bottom surface as illustrated in
In any event, a final memory chip 102 has memory cells 200 that has had particles forcibly migrated into vulnerable areas such that the memory cell 200 fails. The purposeful failure is used to improve the quality of certification testing and capture as failed cells those cells that might pass certification at manufacturing but fail sometime after deployment from the migration of extraneous particles.
It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications, as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
