Patent Application
20060087878
The present invention relates generally to array read access controls, and more particularly, to array read access controls involving the forced pulldown of array readouts from a bitcell.
Standard bitcells and array read access controls are used in data processing systems to perform the function of accepting written data, storing this data in arrays, reading this data and then transforming the data into decoded select signals. There is a constant search to reduce the time delay involved with producing these decoded select signals. Conventional array read access designs consist of a conventional bitcell with a read port followed by specific gating logic to generate the desired multiplexer (MUX) select signals. After a write is performed the bitcell will store the information as data in an array. Then the bitcell produces a readout of this data and that readout will be gated to produce the desired MUX signals. Any operation that is based upon the read result from the bitcell will require additional clock cycles, which increases the time delay of the circuit. If the gate delay stages are reduced, then the array read timing operation becomes less critical and the devices may be sized to achieve greater reliability and/or lower power.
Referring to
The drain of NFET 155 is connected to the source of NFET 170. The read wordline 160 is connected to the gate of NFET 170. The drain of NFET 170 is the read bitline 165. The NFET 170 and the NFET 155 make up the pulldown device 175, and both transistors must be activated before the read bitline 165 will pull down. If NFET 155 is not activated, then the read bitline 165 will maintain its precharged state. The source of NFET 155 is connected to ground 180. The pulldown device 175 allows the signal that has been read to be pulled down as a readout of the read bitline 165. At this point the readout of the bitcell can be gated to produce the MUX select signals.
Referring to
These separate steps lead to a time delay that was previously described. Any operation that requires a readout signal from the bitcell will require additional clock cycles. This result forces array read devices to be designed with timing constraints as the primary issue. If timing issues are less significant, then array read devices can be designed to be smaller in area, more reliable and/or more power efficient. Therefore, there is a need for a method and/or apparatus to modify conventional array read access controls to perform faster.
The present invention provides a method, an apparatus, and a computer program for the reduction of time delay for array read access controls consisting of a bitcell and a pulldown device outside of the bitcell. The pulldown device consists of an nFET transistor that is implemented to pull down a readout from the bitcell. A pulldown signal is generated outside of the array core, and is brought into the array core to activate the pulldown device. Overall, a pulldown of the data array from the bitcell can be accomplished without a complete read of the data array. This reduces the number of stages and the time delay of a data array read. As a result of this time delay reduction, the array read timing operation becomes less critical and the devices may be sized to achieve greater reliability and/or lower power consumption.
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
In the following discussion, numerous specific details are set forth to provide a thorough understanding of the present invention. However, those skilled in the art will appreciate that the present invention may be practiced without such specific details. In other instances, well-known elements have been illustrated in schematic or block diagram form in order not to obscure the present invention in unnecessary detail. Additionally, for the most part, details concerning network communications, electromagnetic signaling techniques, and the like, have been omitted inasmuch as such details are not considered necessary to obtain a complete understanding of the present invention, and are considered to be within the understanding of persons of ordinary skill in the relevant art.
Referring to
A pulsed clock is used as the bitline pulldown signal 320 and the read wordline signal 160. These two signals should be mutually exclusive but they are not required to be. The best embodiment of this device involves separate pulsed clock signals for the bitline pulldown signal 320 and the read wordline signal 160. An extra clock signal must be shaped and staged along with the read wordline signal 160 and the precharge signals to resolve timing issues, such as contention, float, and pulsewidth. In an embodiment, there is only one instance of gating logic outside of the array core that controls the pulldown device 335. This outside gating logic will be used to produce the pulldown signal 320. The physical area of the array core is reduced because the logic gating is outside of the core. The activation of the write wordlines 105 and the read wordlines 160 must be mutually exclusive.
The use of certain logic outside of the array core to control the global read bitlines allows the removal of the dependency on a read of the data array. A 5:1 multiplexer has four of the five select signals stored in the array as 1-hot and the remaining, master select signal existing outside of the array. The values of all five selects must be 1-hot when controlling the multiplexer. Previous methods require reading the data from the array and gating them with the master select signal to ensure the 1-hot condition among all five signals. This modified design controls these bitlines with the pulldown device 335 and the timing dependency on the gating logic can be overridden. Basically, the pulldown device 335 overrides the bitcell 100, and can pull down the bitline regardless of a standard read of the bitcell value. The pulldown device 335 is controlled by a pulldown signal 320 that is produced outside of the array core.
As shown in
Referring to
It is understood that the present invention can take many forms and embodiments. Accordingly, several variations of the present design may be made without departing from the scope of the invention. The capabilities outlined herein allow for the possibility of a variety of programming models. This disclosure should not be read as preferring any particular programming model, but is instead directed to the underlying concepts on which these programming models can be built.
Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Many such variations and modifications may be considered desirable by those skilled in the art based upon a review of the foregoing description of preferred embodiments. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.
