Patent Application
20250126884
The present application relates to manufacturing of semiconductor integrated circuits. More particularly, it relates to a forksheet transistor structure and method of manufacturing the same.
As semiconductor industry moves towards smaller node, field-effect-transistors (FETs) are aggressively scaled to fit into reduced footprint or real estate, which is often dictated by the node size. For example, two nanosheet transistors may be formed directly adjacent a dielectric bar which provides isolation therein-between, which often results in a compact transistor structure.
However, with the dielectric bar directly adjacent to the two nanosheet transistors, that is, directly adjacent to the two set of nanosheets of the two nanosheet transistors with one at a left sidewall and one at a right sidewall of the dielectric bar, it comes with process implication where when the two nanosheet transistors are a same type (e.g., n-type) of transistor and when a pair of different type (e.g., p-type) of transistors (directly adjacent to a neighboring dielectric bar) is formed next to the current pair of transistors, usually no work-function-metal (WFM) undercut suppression may be provided or it is difficult process-wise to provide WFM undercut suppression during a WFM patterning process. On the other hand, when two different types (e.g., one p-type and one n-type) of nanosheet transistors are formed adjacent to the left and right sidewalls of the dielectric bar and when a same type of transistor (from a neighboring dielectric bar) is formed next to a current transistor (of a current dielectric bar) such as, for example, when the two transistors are both p-type transistors, it may require much bigger backside power rails, such as VSS or VDD, to provide power supply to the transistors. This in turn may result in a much tighter spacing between different power rails such as between VSS and VDD in the backside wiring scheme.
Embodiments of present invention provide a semiconductor structure. The structure includes a dielectric bar having a left sidewall and a right sidewall; a first set of nanosheets having a first end and a second end, the second end of the first set of nanosheets directly adjacent to the left sidewall of the dielectric bar; a first conductive layer directly adjacent to the left sidewall of the dielectric bar, the conductive layer surrounding the first set of nanosheets and covering the first end of the first set of nanosheets; and a second set of nanosheets and a second conductive layer, the second conductive layer separating the second set of nanosheets from the right sidewall of the dielectric bar. The dielectric bar and the first set of nanosheets thereby forms a forksheet transistor, which is a type of gate-all-around (GAA) transistor with a forked gate structure.
By having the forksheet transistor formed only at one side, such as the left side, of the dielectric bar, there goes away the necessity for WFM undercut suppression when a different type of forksheet transistor is formed next to the other side, such as the right side, of the dielectric bar. Moreover, because the forksheet transistors are more uniformly spaced with each of them being attached to, directly adjacent to, and/or otherwise in contact with one dielectric bar respectively and being consistently at one side thereof, as is described below in more details, backside power rails of reasonable size may be used to provide power supply to the forksheet transistors, which improves the flexibility of wiring scheme and reduces any chance of short between neighboring backside power rails due to tight spacing that otherwise exists in prior art.
In one embodiment, the structure further includes, with the dielectric bar being a first dielectric bar, a second dielectric bar, where the second dielectric bar has a left sidewall parallel to the right sidewall of the first dielectric bar; the second set of nanosheets has a first end and a second end with the second end of the second set of nanosheets being directly adjacent to the left sidewall of the second dielectric bar; and the second conductive layer is directly adjacent to the left sidewall of the second dielectric bar; surrounds the second set of nanosheets; and covers the first end of the second set of nanosheets.
In another embodiment, the structure further includes a first source/drain (S/D) region next to a first side of the first set of nanosheets, and a first backside contact in conductive contact with a bottom surface of the first S/D region.
In yet another embodiment, the structure further includes a second S/D region next to a first side of the second set of nanosheets, and a second backside contact in conductive contact with a bottom surface of the second S/D region.
In yet one more embodiment, the structure further includes a metal connection on top of the first dielectric bar, the metal connection connects the first conductive layer with the second conductive layer.
In one embodiment, the first conductive layer is a gate metal of an n-type transistor, and the second conductive layer is a gate metal of a p-type transistor; the second dielectric bar has a height higher than a height of the first dielectric bar; and the second dielectric bar has a top surface that is coplanar with a top surface of the metal connection.
In another embodiment, the structure further includes a third dielectric bar; a third set of nanosheets; and a third conductive layer, where the third dielectric bar has a left sidewall and a right sidewall with the right sidewall of the third dielectric bar being parallel to the left sidewall of the first dielectric bar and where the first conductive layer separates the first set of nanosheets from the right sidewall of the third dielectric bar; the third set of nanosheets has a second end directly adjacent to the left sidewall of the third dielectric bar; and the third conductive layer is directly adjacent to the left sidewall of the third dielectric bar and surrounds the third set of nanosheets.
In yet another embodiment, the structure further includes a first mid-of-line (MOL) contact in conductive contact with a top surface of the first conductive layer; a third S/D region next to a first side of the third set of nanosheets; and a second MOL contact in conductive contact with a top surface of the third S/D region.
In yet one more embodiment, the structure further includes a first backside power rail (BSPR) in contact with the first backside contact; a second BSPR in contact with the second backside contact; a backside power distribution network (BSPDN) in contact with the first and the second BSPRs; and a back-end-of-line (BEOL) in contact with the first and the second MOL contact.
Embodiments of present invention further provide a method of forming a semiconductor structure. The method includes forming a dielectric bar between a first stack of nanosheets and a second stack of nanosheets, the dielectric bar having a left sidewall directly adjacent to a second portion of the first stack of nanosheets and a right sidewall directly adjacent to a first portion of the second stack of nanosheets; forming a first set of nanosheets by selectively removing a first portion of the first stack of nanosheets that is not directly adjacent to the left sidewall of the dielectric bar; forming a second set of nanosheets by selectively removing the first portion of the second stack of nanosheets directly adjacent to the right sidewall of the dielectric bar; forming a first conductive layer surrounding the first set of nanosheets and directly adjacent to the left sidewall of the dielectric bar; and forming a second conductive layer surrounding the second set of nanosheets and directly adjacent to the right sidewall of the dielectric bar, the second conductive layer separates the second set of nanosheets from the dielectric bar. By having only the first set of nanosheets attached to the left side of the dielectric bar while the second set of nanosheets being separated from the right side of the dielectric bar, it removes the necessity for WFM undercut suppression, thereby significantly simplifying the manufacturing process, when a different type of forksheet transistor is formed next to the right side of the dielectric bar.
In one embodiment, forming the dielectric bar between the first stack of nanosheets and the second stack of nanosheets includes forming a raw stack of nanosheets; creating a trench opening in the raw stack of nanosheets, the trench opening divides the raw stack of nanosheets into the first stack of nanosheets and the second stack of nanosheets; and filling the trench opening with a dielectric material to form the dielectric bar.
In another embodiment, the method further includes, before forming the second set of nanosheets, forming a sidewall spacer next to the right sidewall of the dielectric bar above the first portion of the second stack of nanosheets; covering a second portion of the second stack of nanosheets with a mask layer; selectively removing the sidewall spacer to expose the first portion of the second stack of nanosheets underneath the sidewall spacer.
In one embodiment, forming the second conductive layer includes selectively removing a sacrificial material between the dielectric bar and the second set of nanosheets to create an opening; selectively removing a set of sacrificial sheets between the second set of nanosheets to create spaces; and filling the opening and the spaces with a conductive material in a replacement-metal-gate process to form the second conductive layer.
In another embodiment, the method further includes lowering a height of the dielectric bar to create an opening between the first conductive layer and the second conductive layer and filling the opening with a conductive material to form a metal connection.
In yet another embodiment, the method further includes forming a backside contact by replacing a placeholder underneath a source/drain (S/D) region, the S/D region being adjacent to a first side of the first set of nanosheets.
In yet one more embodiment, the method further includes forming a mid-of-line (MOL) contact in contact with the first conductive layer surrounding the first set of nanosheets.
The present invention will be understood and appreciated more fully from the following detailed description of embodiments of present invention, taken in conjunction with accompanying drawings of which:
It will be appreciated that for simplicity and clarity purpose, elements shown in the drawings have not necessarily been drawn to scale. Further, and if applicable, in various functional block diagrams, two connected devices and/or elements may not necessarily be illustrated as being connected. In some other instances, grouping of certain elements in a functional block diagram may be solely for the purpose of description and may not necessarily imply that they are in a single physical entity, or they are embodied in a single physical entity.
In the below detailed description and the accompanying drawings, it is to be understood that various layers, structures, and regions shown in the drawings are both demonstrative and schematic illustrations thereof that are not drawn to scale. In addition, for the ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given illustration or drawing. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures. Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.
It is to be understood that the terms “about” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error may be present such as, by way of example only, 1% or less than the stated amount. Likewise, the terms “on”, “over”, or “on top of” that are used herein to describe a positional relationship between two layers or structures are intended to be broadly construed and should not be interpreted as precluding the presence of one or more intervening layers or structures.
Moreover, although various reference numerals may be used across different drawings, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, or structures, and thus detailed explanations of the same or similar features, elements, or structures may not be repeated for each of the drawings for economy of description. Labelling for the same or similar elements in some drawings may be omitted as well in order not to overcrowd the drawings.
For example,
Embodiments of present invention provide forming a semiconductor structure 10 by receiving or providing a semiconductor substrate 100. The semiconductor substrate 100 may include a bulk silicon (Si) substrate 101, an etch-stop layer 102 on top of the Si substrate 101, and a Si layer 103 on top of the etch-stop layer 102. In one embodiment, the etch-stop layer 102 may be a silicon-germanium (SiGe) layer to contain a first percentage level of germanium (Ge) such as, for example, 25 at. %, which may be referred to as a SiGe25 layer. Therefore, the etch-stop layer 102 may sometimes be a SiGe25 layer. In another embodiment, the semiconductor substrate 100 may be a silicon-on-insulator (SOI) substrate with an insulating layer such as a silicon-oxide (SiO2) layer or silicon-nitride (SiN) layer between the Si layer 103 and the bulk substrate 101. The insulating layer may work as an etch-stop layer.
Embodiments of present invention further provide forming a raw stack of nanosheets 200 on top of the Si layer 103 to form one or more nanosheet transistors and forming a hard mask layer 201 on top of the raw stack of nanosheets 200. In one embodiment, as being described below in more details, the raw stack of nanosheets 200 may include a raw stack of blanket Si nanosheets alternating with a raw stack of blanket sacrificial sheets. The hard mask layer 201 may be formed such that it has a height H1 ranging from about 30 nm to about??? 100 nm. The hard mask layer 201 may be formed of SiN, SiBCN, SiCN, SiOCN, SiCO, SiC, AIOx, TiOx, AlNx, or combination of those layers, etc.
The pattern of the hard mask 202 may be transferred into the raw stack of nanosheets 200 through a selective etching process, thereby transforming the raw stack of nanosheets 200 into one or more stacks of nanosheets 210. For example, the one or more stacks of nanosheets 210 may include a first, a second, a third, and a fourth stack of nanosheets 261, 262, 263, and 264. Each stack of nanosheets 261, 262, 263, and 264 may include a stack of Si nanosheets 211 separated by and/or alternating with a stack of sacrificial sheets 212. In one embodiment, the stack of Si nanosheets 211 may be made of silicon, and the stack of sacrificial sheets 212 may be made of SiGe to include a second percentage level of Ge ranging from 30 at. % to 65 at. %, for example. The sacrificial sheets 212 thus may be referred to as a stack of SiGeXX sheets with XX representing the percentage of Ge such as a stack of SiGe30 sheets or a stack of SiGe65 sheets. The inclusion of Ge in the stack of sacrificial sheets 212 enables a selective etching process during which the stack of sacrificial sheets 212 may be selectively removed in a replacement-metal-gate (RMG) process as being described below in more details.
In transforming the raw stack of nanosheets 200 into the one or more stacks of nanosheets 210, the selective etching process may create one or more trench openings between the one or more stacks of nanosheets 210. For example, a first trench opening 251 may be created between the first and the second stack of nanosheets 261 and 262; a second trench opening 252 may be created between the second and the fourth stack of nanosheets 262 and 264; and a third trench opening 253 may be created between the third and the first stack of nanosheets 263 and 261. The first, the second, and the third trench opening 251, 252, and 253 may start from the hard mask 202, through the raw stack of nanosheets 200, and be made sufficiently deep and partially into the Si layer 103 of the semiconductor substrate 100. The first, the second, and the third trench opening 251, 252, and 253 may be used for forming one or more dielectric bars as being described below in more details.
The RIE process may also transform the one or more stacks of nanosheets 210, that is the second portion of the one or more stacks of nanosheets 210, into one or more raw sets of nanosheets 220. Each of the one or more raw sets of nanosheets 220 may include a raw set of Si nanosheets 221 separated by and/or alternating with a raw set of sacrificial sheets 222. The one or more raw sets of nanosheets 220, in particular the raw set of Si nanosheets 221, may be directly adjacent to the left sidewalls of the one or more dielectric bars such as the first, the second, and the third dielectric bar 301, 302, and 303. In the meantime, the raw set of Si nanosheets 221 may be separated from the right sidewalls of the first, the second, and the third dielectric bar 301, 302, and 303 by the set of openings 342.
Using the set of dummy gates 610 as a mask, embodiments of present invention provide recessing the one or more raw sets of nanosheets 220 to create openings between the set of dummy gates 610, thereby transforming or truncating each of the one or more raw sets of nanosheets 220 into one or more sets of nanosheets 230 underneath each of the set of dummy gates 610. In other words, the one or more raw sets of nanosheets 220 may be patterned into a plurality of one or more sets of nanosheets 230. Each of the set of nanosheets 230 may include a set of Si nanosheets 231 and a set of sacrificial sheets 232, and the set of Si nanosheets 231 may be separated by or alternating with the set of sacrificial sheets 232.
Embodiments of present invention provide further recessing the Si layer 103 exposed by the recessing of the one or more raw sets of nanosheets 220 to create openings in the Si layer 103 between the set of dummy gates 610. The recessing may, to certain extent, remove a portion of the one or more dielectric bars in the region between and not covered by the set of dummy gates 610. Subsequently, embodiments of present invention provide filling the openings with a sacrificial material such as, for example, epitaxial SiGe or dielectric material, to form one or more placeholders (PHs) such as a first PH 411 between the third dielectric bar 303 and the first dielectric bar 301, and a second PH 421 between the first dielectric bar 301 and the second dielectric bar 302. for forming backside contacts later in the process. The PHs such as the first PH 411 and the second PH 421 may be used for forming backside contacts as being described below in more details.
After forming the PHs, inner spacers may be formed at the ends of the set of sacrificial sheets 232. Source/drain (S/D) regions may be formed between the set of dummy gates 610 and from the sidewalls of the one or more sets of nanosheets 230, particularly from the sidewalls of the set of Si nanosheets 231 while the set of sacrificial sheets 232 are covered by the inner spacers. For example, a n-type S/D region 511 may be epitaxially grown therefore formed above the first PH 411 and in the region between the third dielectric bar 303 and the first dielectric bar 301. Further for example, a p-type S/D region 521 may be formed above the second PH 421 and in the region between the first dielectric bar 301 and the second dielectric bar 302. The n-type S/D region 511 and the p-type S/D region 521 may be formed directly adjacent to the sidewalls of the one or more sets of nanosheets 230. Additional S/D regions such as a n-type S/D region 512 and a p-type S/D region 522 may be formed.
Embodiments of present invention further provide performing a replacement-metal-gate (RMG) process to form nanosheet transistors by first selectively removing material of the set of dummy gates 610, selectively removing the set of sacrificial sheets 232 between the set of Si nanosheets 231 of the one or more sets of nanosheets 230 to create spaces, and selectively removing the sacrificial fillers 223 that separate the one or more dielectric bars from the one or more sets of nanosheets 230 to create openings.
The first and the second n-type nanosheet transistor 631 and 633 and the first and the second p-type nanosheet transistor 632 and 634 may each be referred to as a forksheet transistor. A forksheet transistor may be considered as a type of gate-all-around (GAA) transistor with a forked gate structure. The set of Si nanosheets 231 of each of the forksheet transistors may be directly adjacent to, attached to, and/or in contact with only one side of the dielectric bars respectively, and preferably consistently. By having the forksheet transistors formed only at one side, such as a left side, of the dielectric bars, it removes the necessity for having WFM undercut suppression during a manufacturing process when a different type of forksheet transistor is formed next to the other side, such as a right side, of the dielectric bars. Moreover, because the forksheet transistors are more uniformly spaced with each of them being attached to, directly adjacent to, and/or otherwise in contact with one dielectric bar respectively and being consistently at one side thereof, backside power rails of reasonable size may be used to provide power supply to the forksheet transistors. This in-turn improves the flexibility of wiring scheme and reduces any chance of short between neighboring backside power rails due to, for example, tight spacing otherwise found in prior art.
Following the formation of various MOL contacts, embodiments of present invention provide forming a back-end-of-line (BEOL) structure 720 on top of and in contact with the one or more MOL contacts. The BEOL structure 720 may provide signal routing and/or power supply functions for the underneath one or more nanosheet transistors. Next, a carrier wafer 730 may be bonded onto the BEOL structure 720 such that the semiconductor structure 10 may be flipped upside down for further processing from the backside of the semiconductor substrate 100.
It is to be noted here that upside-up (instead of upside-down) drawings will continue to be used hereinafter for
After forming the first and the second backside contacts 431 and 441, additional dielectric layer such as a backside interlevel dielectric (BILD) layer 820 may be deposited on top of the BILD layer 810 covering the backside contacts 431 and 441. In one embodiment, the BILD layer 820 may include a same material as the BILD layer 810. One or more backside power rails (BSPR's) such as a first BSPR 821 and a second BSPR 822 may be formed in the BILD layer 820. After forming the first and the second BSPR 821 and 822, additional structures such as a backside power distribution network (BSPDN) 830 may be formed on top of one or more BSPRs to be in conductive contact with, for example, the first and the second BSPR 821 and 822 for power distribution.
It is to be understood that the exemplary methods discussed herein may be readily incorporated with other semiconductor processing flows, semiconductor devices, and integrated circuits with various analog and digital circuitry or mixed-signal circuitry. In particular, integrated circuit dies can be fabricated with various devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, etc. An integrated circuit in accordance with the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.
Accordingly, at least portions of one or more of the semiconductor structures described herein may be implemented in integrated circuits. The resulting integrated circuit chips may be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip may be mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other high-level carrier) or in a multichip package (such as a ceramic carrier that has surface interconnections and/or buried interconnections). In any case the chip may then be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product, such as a motherboard, or an end product. The end product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of various embodiments of present invention have been presented for the purposes of illustration and they are not intended to be exhaustive and present invention are not limited to the embodiments disclosed. The terminology used herein was chosen to best explain the principles of the embodiments, practical application or technical improvement over technologies found in the marketplace, and to enable others of ordinary skill in the art to understand the embodiments disclosed herein. Many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. Such changes, modification, and/or alternative embodiments may be made without departing from the spirit of present invention and are hereby all contemplated and considered within the scope of present invention. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the spirit of the invention.
