BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A and 1B are two cross sectional views of two alternate prior art semiconductor devices manufactured by using double polysilicon layers process in forming the metal-insulator-polysilicon (MIP) structure.
FIG. 2 is a cross sectional view of a semiconductor device with new device configuration and manufacturing processes of this invention.
FIGS. 3A to 3G are a serial of cross sectional views for showing the manufacturing processes of a semiconductor device shown in FIG. 2 of this invention.
DETAILED DESCRIPTION OF THE METHOD
Referring to FIG. 2 for a cross sectional view of a semiconductor device 100. The semiconductor device 100 is supported on a substrate 105 formed with a field oxide layer 110. The field oxide layer is formed adjacent to a transistor area. The top surface of the field oxide layer 110 is to support resistor and capacitor. On the top surface of the transistor area, a transistor is formed with a polysilicon gate 120-G disposed on top of a gate oxide layer 115 between a source region 140-S and a drain region 140-D. The gate is surround by a spacer layer 130-G. The transistor is further provided with a ESD protection layer 150-ESD formed on top of a N+ or P+ diffusion resistor layer 140-S or 140-D that in turn is connected to a tungsten plug 180 filled in a trench opened through an zero void inter-layer dielectric (ILD0) layer 170.
A capacitor is supported on the top surface of the field oxide layer 110 that includes a N+ doped polysilicon layer 120-C to function as the bottom conductive layer. A spacer layer 130-C surrounds the doped polysilicon layer 120-C. An insulation salicide block (SAB) layer 150-C-I covers a section of the spacer 130-C to insulate the capacitor from the transistor. The capacitor further includes a dielectric layer 150-C formed as a SAB layer and covered by a top conductive layer 160. In an exemplary embodiment, the top conductive layer is a Ti/TiN layer that is in electrical connection with one of the tungsten plugs 180. Furthermore, a portion of the top surface of the N+ doped polysilicon layer 120 is covered by a TiSi2 conductive layer 145 that is in contact with another tungsten plug 180. The capacitor is therefore configured with a metal-insulator-polysilicon (MIP) that has a single polysilicon structure.
On the top surface above the field oxide layer 110 is also a resistor that includes a high resistive element formed by a doped polysilicon segment 120-R. On both end of the polysilicon resistive element 120-R are contact head 125 formed by N+ doped segments of the polysilicon segment. On top of the contact head 125 is also a TiSi conductive layer 145 in electric contact with tungsten plugs 180 formed in the trenches opened through the ILD0 layer 170. The resistor is further insulated form the capacitor by the spacer layer 130-R surrounding the polysilicon segment 120-R. High sheet resistance of the resistor is achieved by a differenetial doping into the polysilicon segment 120-R as will be further discussed below.
The device configuration as shown in FIG. 2 is manufactured with single polysilicon process. A simplified manufacturing process is therefore disclosed. The device further provides manufacturing flexibility to control the resistance by controlling the dopant concentration of the polysilicon segments of 120-R and 120-C, and control the capacitance by controlling the material type and thickness of layer 150-C. High resistance and capacitance may be conveniently achieved to provide useful device components that can be conveniently implemented in either the analog or power integrated circuit (IC) device applications.
According to above descriptions, this invention discloses a semiconductor device that includes a transistor, a capacitor and a resistor. The capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a conductive layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. In a preferred embodiment, the polysilicon layer is differentially doped to form the high sheet rho resistor of the semiconductor device. In another preferred embodiment, the polysilicon layer further doped with transistor gate doping ions to form a gate for the transistor of the semiconductor device. In another preferred embodiment, the transistor further includes a gate polysilicon and the resistor further includes a doped polysilicon resistor, wherein the gate polysilicon, the doped polysilicon resistor and the doped polysilicon layer functioning as a bottom conductive layer of the capacitor are formed by one polysilicon deposition process and disposed substantially on a same vertical level in the semiconductor device. In another preferred embodiment, the capacitor and resistor are disposed on a field oxide layer adjacent to the transistor. In another preferred embodiment, the transistor further includes an electrostatic discharge (ESD) protection layer formed on top of a N+ or P+ diffusion resistor layer electrically connected to a source or a drain region of the transistor. The TiSi2 layer is further electrically connected to a tungsten plug filled in a trench opened through the 1st inter-layer dielectric (ILD0) layer covering the semiconductor device. In another preferred embodiment, the doped polysilicon layer of the capacitor includes a N+ doped polysilicon layer to function as a bottom conductive layer. In another preferred embodiment, the capacitor further includes a spacer surrounding and insulating the doped polysilicon layer to function as a bottom conductive layer. In another preferred embodiment, the top conductive layer of the capacitor further includes a Ti/TiN layer to function as a top conductive layer and is electrically connected to a tungsten plug filling in a trench opened through the inter-layer dielectric (ILD0) layer covering the semiconductor device. In another preferred embodiment, the resistor includes a high resistive element includes a doped resistive polysilicon segment wherein both ends of the resistive polysilicon element includes contact head segments with N+ doped-and-salicided. The contact head segments are further in contact with a tungsten plug filling in a trench opened through the inter-layer dielectric (ILD0) layer covering the semiconductor device. In another preferred embodiment, the resistor further includes a spacer layer for surrounding and insulting the high resistive element from the capacitor.
Referring to FIGS. 3A to 3G for a serial of side cross sectional views to illustrate the fabrication steps of a device of FIG. 2 that includes a high sheet resistance resistor and a high capacitance capacitor formed with a single polysilicon process. In FIG. 3A, a local oxidation of silicon (LOCOS) process or a shallow trench insulation (STI) process is employed to form the field oxide 210 in a substrate 205. An optional well implant is carried out followed by a gate oxidation to form the gate oxide layer 215. Then a polysilicon layer 220 is deposited on the top surface. In FIG. 3B, an dopant implant is performed with light dose of phosphorus to adjust the resistance of the polysilicon layer 220 followed by a polysilicon annealing process. In FIG. 3C, a gate mask (not shown) is applied to etch the polysilicon layer 220 into a transistor gate 220-G, a capacitor-polysilicon segment 220-C and a resistor-polysilicon segment 220-R. A lightly doped drain (LDD) mask (not shown) is employed to perform a light doped drain implant to form LDD regions of the transistor. Then a spacer layer deposition is carried out followed by an etch process to form spacers 230-G around the gate polysilicon 220-G, spacers 230-C around the capacitor-polysilicon segment 220-C and spacers 230-R around the resistor-polysilicon segment 220-R. A source/drain mask (not shown) is employed to carry out a source drain implant followed by applying an elevated temperature to activate the source and drain regions 240-S and 240-D respectively. The source-drain implant process achieves N+ doping the NMOS gate or P+ doping the PMOS gate 220-G. The source-drain implant process further accomplishes the N+ doping the bottom plate of the capacitor polysilicon segment 220-C and N+ doping the high resistance (HR) head contact regions 225. In FIG. 3D, a salicide block (SAB) layer deposition is carried out to deposit an insulator layer over the top surface. Then, a SAB mask (not shown) is applied to pattern the SAB layer into an ESD diffusion resistor segment 250-EDS, a capacitor insulting segment 250-C and a resistor segment 250-R. This SAB layer may be any high quality insulator to suit the specific capacitance requirements such as HTO, ONO stacked layers, oxynitride or high K dielectric layer.
In FIG. 3E, a Ti/TiN layer is deposited and a first rapid thermal activation (RTA) process is carried out to form a TiSi layer 245 at the transistor source and drain regions and the gate regions. The TiSi layer 245 is also formed in the HR head contact regions and the contact region of the capacitor bottom plate. Then a metal insulator polysilicon (MIP) mask 255 is employed and the un-reacted Ti/TiN is removed by the use of APM followed by the HPM solution in the etch process. The MIP mask 255 protects the Ti/TiN layer 260 to function as the top plate for the capacitor above the capacitor insulator segments 250-C. In FIG. 3F, the MIP mask 255 is removed and a second rapid thermal activation process is performed to convert the TiSi layer 245 into low-resistivity TiSi2 layer 245 (260 is still Ti/TiN layer). In FIG. 3G, the first interlayer dielectric layer (ILD0) layer 270 is deposited and planarized. Contact trenches are opened through the ILD0 layer 270 and filled with tungsten plugs 275 in each of these trenches to contact the TiSi2 layer 245 on top of the source and drain. The tungsten plugs 280 further contact the top and bottom plates of the capacitor and the contact heads 225 of the resistor. Then the manufacturing processes are completed with the standard back-end of the line (BEOL) processes.
According to FIGS. 3A to 3G, this invention further discloses a method of manufacturing a semiconductor device. The method includes a step of depositing a polysilicon layer on top of a semiconductor substrate followed by patterning and doping the polysilicon layer into a transistor gate, a bottom conductive layer for a capacitor and a resistor segment. The method further includes a step of forming the capacitor by depositing and patterning an insulator layer to function as a capacitor dielectric layer on top of the bottom conductive layer of the capacitor followed by depositing, patterning and annealing a Ti/TiN layer as a conductive layer to form a top conductive layer for the capacitor thus forming the capacitor as a single polysilicon layer metal-insulator-polysilicon (MIP) structure. In a preferred embodiment, the step of depositing and patterning an insulator layer includes a step of depositing and patterning a salicide block (SAB) layer to function as a capacitor dielectric layer on top of the bottom conductive layer of the capacitor. In another preferred embodiment, the step of depositing and patterning an insulator layer includes a step of depositing and patterning a high temperature oxide (HTO) layers to function as a capacitor dielectric layer on top of the bottom conductive layer of the capacitor. In another preferred embodiment, the step of depositing and patterning an insulator layer includes a step of depositing and patterning an silicon oxide-silicon nitride and silicon oxide (ONO) stack layers to function as a capacitor dielectric layer on top of the bottom conductive layer of the capacitor. In another preferred embodiment, the step of depositing and patterning an insulator layer includes a step of depositing and patterning a silicon oxyntirde to function as a capacitor dielectric layer on top of the bottom conductive layer of the capacitor. In another preferred embodiment, the method further includes a step of applying a local oxidation silicon (LOCOS) process to form a field oxide for depositing the polysilicon layer thereon for patterning the polysilicon layer into the bottom conductive layer for a capacitor and the resistor segment. In another preferred embodiment, the method further includes a step of applying a differential doping to increase the resistance of the polysilicon layer followed by a polysilicon annealing process. In another preferred embodiment, the method further includes a step of applying a source/drain mask to carry out a source drain implant followed by applying an elevated temperature to activate a source and a drain region. In another preferred embodiment, the step of carrying out a source drain implant further includes a step of doping the transistor gate and doping a portion of the resistor segment to function as resistor contact region. In another preferred embodiment, the step of depositing and patterning an insulator layer to function as a capacitor dielectric layer further includes a step of depositing a salicide block (SAB) layer followed by patterning the SAB layer into the dielectric layer for the capacitor. In another preferred embodiment, the step of depositing and patterning the SAB layer further includes a step of patterning the SAB layer into an ESD segment. In another preferred embodiment, the step of depositing and patterning the SAB layer further includes a step of patterning the SAB layer into an insulation layer covering the resistor segment. In another preferred embodiment, the step of depositing, patterning and annealing the Ti/TiN layer further includes a step of forming head contact regions for the resistor segment and a contact region for the capacitor bottom formed by the polysilicon layer. In another preferred embodiment, the step of depositing, patterning and annealing the Ti/TiN layer further includes a step of removing an un-reacted Ti/TiN for patterning a top surface above the SAB layer of the capacitor to form the single polysilicon MIP structure. In another preferred embodiment, the method further includes a step of applying a second rapid thermal activation process to form a TiSi2 layer to function as contacts for the drain and source regions, the top capacitor surface and the contact head of the resistor segment. In another preferred embodiment, the method further includes a step of forming a first interlayer dielectric layer (ILD0) covering the semiconductor device and opening contact openings on top of the contacts composed of the TiSi2. In another preferred embodiment, the method further includes a step of filling the contact openings with a tungsten contact plug for contacting the contacts formed with the TiSi2.
Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is not to be interpreted as limiting. Various alterations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention.
Patent Application
20070281418
