FORMATION OF SILICIDED SURFACES FOR SILICON/CARBON SOURCE/DRAIN REGIONS

Abstract

Formation of a silicide layer on the source/drain regions of a field effect transistor with a channel under tensile strain is disclosed. The strain is originated by the silicon/carbon source/drain regions which are grown by CVD deposition. In order to form the silicide layer, a silicon cap layer is deposited in situ by CVD. The silicon cap layer is then employed to form a silicide layer made of a silicon/cobalt compound. This method allows the formation of a silicide cobalt layer in silicon/carbon source/drain regions, which was until the present time not possible.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

FIG. 1 schematically shows a cross-sectional view of a transistor element with a channel region under tensile strain and a silicide layer over the source/drain regions, according to an illustrative embodiment of the present invention;

FIGS. 2 a-2e schematically show the fabrication process of a silicide layer for a transistor element with a channel region under tensile strain, wherein the source/drain regions are made of silicon/carbon, according to illustrative embodiments of the present invention;

FIG. 3 schematically shows a cross-sectional view of a transistor element according to an embodiment of the present invention, wherein an intermediate layer is located between the silicide layer and the silicon/carbon layer; and

FIG. 4 schematically shows a cross-sectional view of a transistor element according to an embodiment of the present invention, wherein the transistor channel is under tensile strain originated by the source/drain regions, which are completely embedded in the active layer of the transistor element.

Claims

1. A method, comprising: forming a recess adjacent to a gate electrode of a transistor;forming a semiconductor layer in said recess which produces a tensile strain in the channel region of said transistor;forming a cap layer on said semiconductor layer; andforming a silicided layer in said cap layer.

2. The method of claim 1, wherein said cap layer is formed by selective epitaxial growth.

3. The method of claim 1, wherein said semiconductor layer in said recess is formed by selective epitaxial growth.

4. The method of claim 1, wherein said semiconductor layer in said recess and said cap layer are grown in situ.

5. The method of claim 1, wherein said cap layer is formed by deposition of a silicon layer.

6. The method of claim 1, wherein forming of said silicided layer comprises the deposition of a metal layer.

7. The method of claim 6, wherein said deposition of said metal layer is followed by a rapid thermal anneal.

8. The method of claim 6, wherein said metal layer is a cobalt layer.

9. The method of claim 1, wherein said semiconductor layer in said recess is formed by selective epitaxial growth.

10. The method of claim 1, wherein said cap layer is substantially completely converted in a silicide.

11. The method of claim 1, wherein part of said cap layer is not silicided.

12. The method of claim 1, wherein said cap layer can be in situ doped.

13. The method of claim 1, wherein said silicided layer can be in situ doped.

14. The method of claim 1, wherein said semiconductor layer is a silicon/carbon layer with approximately 1 atomic percent carbon or more.

15. A transistor element, comprising: a strained channel region; andsource/drain regions formed in a crystalline semiconductor layer and comprising a first and a second layer, said first layer generating tensile strain in said strained channel region due to the lattice mismatch between said first layer and said channel region and second layer being silicided.

16. The transistor element of claim 15, wherein said source/drain regions are raised regions.

17. The transistor element of claim 15, wherein said first layer comprises silicon and carbon.

18. The transistor element of claim 17, wherein the percentage of carbon in said first layer is 1% or higher.

19. The transistor element of claim 15, wherein said second layer comprises a silicon cobalt compound.

20. The transistor element of claim 15, wherein said second layer has an amorphous structure.

21. The transistor element of claim 15, wherein said transistor is an N-type field effect transistor.

22. The transistor element of claim 15, wherein the source and drain regions comprise a third layer located between the first and the second layers.

23. The transistor element of claim 22, wherein said third layer is a silicon layer.