Patent Application
20200091449
The production of a stack of layers together defining one or more electronic devices involves the inclusion within the stack of a dielectric for the one or more electronic devices.
The inventors for the present application have conducted extensive research around forming dielectrics for electronic devices, and have found techniques capable of improving yield.
There is hereby provided a method of forming a stack of layers defining one or more electronic devices, the method comprising: depositing a first thickness of curable, dielectric or dielectric precursor material over an area of a workpiece; thereafter exposing the workpiece to curing conditions at least over said area of said workpiece; and without any intermediate patterning operation, thereafter depositing a second thickness of said curable material over said area of said workpiece; and thereafter again exposing the workpiece to curing conditions at least over said area of said workpiece.
According to one embodiment, said one or more electronic devices include one or more transistors and said dielectric or dielectric precursor material is a gate dielectric or gate dielectric precursor material.
According to one embodiment, exposing the workpiece to curing conditions comprises exposing the workpiece to curing radiation at least over said area of said workpiece.
According to one embodiment, the first and second thicknesses are substantially equal.
According to one embodiment, the curable material is a cross-linkable material, and the curing radiation is at one or more wavelengths that induce cross-linking of the cross-linkable material.
According to one embodiment, the method comprises: after said first curing and before depositing said second thickness of said curable material, subjecting the workpiece to a surface treatment at least over said area of said workpiece.
According to one embodiment, the method comprises: depositing said second thickness of curable material comprises forming a film of a solution of said curable material; and said surface treatment increases the wettability of the surface of the workpiece for said solution of said curable material over said area of said workpiece.
According to one embodiment, said surface treatment comprises exposing the workpiece to a plasma or ultraviolet radiation from an ultraviolet lamp, at least over said area of said workpiece.
According to one embodiment: before depositing said first thickness of curable material, the workpiece includes a semiconductor channel material layer providing the semiconductor channels for said one or more transistors.
According to one embodiment: said semiconductor channel material layer is a patterned layer: forming said patterned semiconductor channel material layer comprises patterning a layer of semiconductor channel material via a dielectric layer; and the method comprises depositing said first thickness of said curable material on said dielectric layer.
There is also hereby provided a method of forming a stack of layers defining one or more electronic devices, the method comprising: depositing a controlled amount of a solution of dielectric material or dielectric precursor material on a workpiece over an area of the workpiece, and thereafter depositing a second controlled amount of said solution of a dielectric material or a dielectric precursor material on the workpiece over said area of the workpiece; wherein prior to depositing said second controlled amount of said solution of dielectric material or dielectric precursor material, subjecting the workpiece to a surface treatment so as to increase the wettability of the surface of the workpiece for said solution of gate dielectric material or gate dielectric precursor material over said area of the workpiece.
According to one embodiment, said one or more electronic devices include one or more transistors and said dielectric or dielectric precursor material is a gate dielectric or gate dielectric precursor material.
According to one embodiment, said surface treatment comprises exposing said workpiece to a plasma or ultraviolet radiation from an ultraviolet lamp.
An embodiment of the present invention is described in detail hereunder, by way of example only, with reference to the accompanying drawings, in which:
A first embodiment of the invention is described in detail below for the example of forming the dielectric for a top-gate transistor device, but the technique is equally applicable to the formation of a dielectric for a bottom-gate transistor device, and to the formation of dielectrics for other types of electronic device that rely on capacitive coupling via a dielectric, such as capacitor devices.
A first embodiment of the invention is described in detail below for the example of forming an array of transistors for controlling an array of pixel electrodes, but the technique is equally applicable to the formation of one or more electronic devices for other functions, such as e.g. transistors and/or capacitors for a logic circuit.
A first embodiment of the invention is described in detail below for the example of forming a gate dielectric over a semiconductor channel material layer patterned via an additional gate dielectric layer, but the technique is equally applicable to the formation of a gate dielectric over a semiconductor channel material layer patterned other than via an additional gate dielectric layer, and to the formation of a gate dielectric over an unpatterned semiconductor channel material layer.
A first embodiment of the invention is described for the example of forming a gate dielectric for one or more transistors including an organic semiconductor channel (referred to as organic thin film transistors (OTFTs)), but the technique is equally applicable to the formation of a gate dielectric for one or more transistors including other types of semiconductor channels.
The first embodiment involves the formation in situ on a (e.g. plastics) support film of a stack of conductor, semiconductor and dielectric layers that together define one or more transistors, such as for example, an array of transistors.
A solution of organic polymer semiconductor channel material is deposited substantially uniformly over a workpiece including the above-described source-drain conductor pattern, by e.g. a spin-coating technique, to form a continuous/unpatterned layer 8a. The formation of this continuous layer 8a of semiconductor channel material may, for example, be preceded by the formation on the source-drain conductor pattern of a self-assembled monolayer of organic material that facilitates the transfer of charge carriers between the source-drain conductor pattern and the semiconductor channel material.
A solution of a dielectric material (or a precursor to a dielectric material) is deposited substantially uniformly over the resulting workpiece (including the continuous layer 8a of organic semiconductor channel material, by e.g. a spin-coating technique, to form a continuous/unpatterned layer. In this example, there is used a curable dielectric material having a lower dielectric constant than the dielectric material deposited later, as discussed below.
The continuous layer 10a of curable dielectric material is patterned by the curing of selective regions of the continuous layer 10a, and developing of the latent solubility image thus created in the continuous layer 10a, to create a mask 10b for patterning the continuous layer of semiconductor channel material 8a by e.g. a reactive ion etching technique. The selective curing of the continuous layer 10a comprises exposing the continuous layer 10a through a patterned photomask to radiation at a wavelength that induces cross-linking in the curable material, which cross-linking reduces solubility in the solvent from which the curable material was deposited.
A controlled amount of a solution of a cross-linkable material is deposited substantially uniformly over an area of the upper, working surface of the resulting workpiece including the patterned semiconductor and dielectric layers 8b, 10b, by e.g. a spin-coating technique, to form a continuous layer 12a. As mentioned below in relation to
The resulting workpiece is subjected to a baking process to remove solvent and then exposed over at least the area of the continuous layer 12a (and from the side of the workpiece on which the continuous layer 12a was formed) to curing radiation at one or more wavelengths (e.g. ultraviolet (UV) radiation) that induce cross-linking of the cross-linkable material. The resulting workpiece is then subjected to a surface treatment over at least the area of the cured continuous gate dielectric layer 12b, which surface treatment enhances the wettability of the surface of the cured, dielectric layer 12b for the same solution of cross-linkable material. This surface treatment may, for example, involve exposing the workpiece to a plasma (such as an argon plasma) at least over the area of the cured dielectric layer 12b, or exposing the workpiece to ultraviolet (UV) radiation from a UV lamp (e.g. UV at about 254 nm or UV Ozone at about 185 nm), at least over the area of the cured dielectric layer. In this example, the work piece is subject to an additional bake to finish the curing process.
Without any intermediate patterning of the cured and surface-treated dielectric layer 12c (i.e. with retention of the first gate dielectric layer over the whole area over which the solution of the curable material was deposited), without any deposition of any intervening layer, a second controlled amount of the exact same solution of cross-linkable material is deposited substantially uniformly over the same area of the workpiece over which the first controlled amount of the solution of cross-linkable material was deposited, to form a continuous layer 14a directly on the cured and surface-treated dielectric layer 12c. The deposition conditions and deposition technique are the same as for the deposition of the first controlled amount of the solution of cross-linkable material; for example, the same spin-coating technique may be used.
The resulting workpiece is subjected to a baking process to remove solvent, and then exposed over at least the area of the continuous layer 14a (and from the side of the workpiece on which the continuous layer 14a was formed) to curing radiation at one or more wavelengths (e.g. ultraviolet (UV) radiation) that induce cross-linking of the cross-linkable material. In this example, the work piece is again subject to an additional bake to finish the curing process.
Immediately after curing, the resulting cured, dielectric layer 14b occupies substantially all regions occupied by the underlying cured and surface-treated dielectric layer 12c; there are substantially no regions of the workpiece occupied by only one of the two gate dielectric layers 12c, 14b. The technique does not exclude patterning of one or both of the two gate dielectric layers 12c, 14b after the second curing operation, but no patterning of the lower gate dielectric layer is done before forming the upper gate dielectric layer.
In this example, conductor material is deposited substantially uniformly over the upper, working surface of the resulting workpiece, including the upper, cured gate dielectric layer 14b, by e.g. a vapour deposition technique such as sputtering, to form a continuous layer. The continuous layer of conductor material is patterned (by e.g. a photolithographic technique using a temporary resist) to define one or more gate conductors 16 providing the gate electrodes for the one or more transistors. According to another example, a gate conductor pattern is formed by a printing technique.
In the example mentioned above of producing an active-matrix array of transistors, the patterned conductor layer defines an array of gate conductors, each providing the gate electrode for a respective column of transistors of the array of transistors, and each extending beyond the array of transistors. Each drain conductor (which may, for example, form a pixel electrode or be conductively connected to a respective pixel electrode at a higher level within the stack) is associated with a respective unique combination of gate and source conductors, and is independently addressable via the portions of the gate and source conductors outside the array of transistors. As mentioned above, this technique is equally applicable to the formation of transistors with other functions, such as transistors for a logic circuit, in which the electrical contacts may (or may not) be within a circuit area including transistors.
With reference to
The inventors for the present application have found that the above-described technique results in a production process with better yield, compared to an otherwise identical technique in which the two gate dielectric layers 12c, 14b having the same composition are replaced by a single upper gate dielectric layer having the same composition as the two upper gate dielectric layers 10b, 12c and having substantially the same thickness as the combined thickness of the two upper gate dielectric layers 12c, 14b. The inventors for the present application have attributed this improvement in yield to two factors: (i) better cross-linking of the cross-linkable material; and (ii) a reduction in the contribution by pinholes in the gate dielectric to leakage currents between the semiconductor and the gate electrode. For the latter, the inventors for the present application believe that the above-described surface treatment of the upper surface of the lower one of the two gate dielectric layers has the effect of better preventing the propagation of pinholes (arising from the solution deposition process) in the lower one of the two gate dielectric layers into and through the upper one of the two gate dielectric layers.
The above-mentioned improvement in cross-linking may also be achieved to some extent when performing curing other than via an irradiative technique, such as a thermal curing technique involving heating the workpiece by thermal conduction.
Electronic devices (such as e.g. transistors, transistor arrays and/or capacitors) produced by the technique described above may be used in a wide range of devices, such as e.g. display devices, sensor devices and logic circuits.
In addition to any modifications explicitly mentioned above, it will be evident to a person skilled in the art that various other modifications of the described embodiment may be made within the scope of the invention.
The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole in the light of the common general knowledge of a person skilled in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein, and without limitation to the scope of the claims. The applicant indicates that aspects of the present invention may consist of any such individual feature or combination of features.
| Number | Date | Country | Kind |
|---|---|---|---|
| 1815017.7 | Sep 2018 | GB | national |
