Patent Application
20230215727
During fabrication of integrated circuits (ICs), a top metallization layer is added and etched to form metal portions that will be used as bond pads to access the IC. Typically, after this stage of IC fabrication, a passivation stack is deposited on the ICs to protect the IC from amongst things such as electrostatic discharge, unwanted debris and so forth. If the passivation stack thickness across a die has high variation, then there may be process issues. For example, if the passivation stack is too thick it will take longer to etch a via to the bond pads. In another example, if the passivation stack is too thin, then some portions of the IC may become over-etched (e.g., portions of the bond pad are etched away).
In one aspect, a method includes depositing a first glass layer on a metallization layer and depositing an etch stop layer on the first glass layer. The method further includes depositing a second glass layer on the etch stop layer and polishing the second glass layer down to at least a surface of the etch stop layer.
In another aspect, an integrated circuit (IC) includes a metallization layer and a passivation stack on the metallization layer. The passivation stack includes an etch stop layer.
The foregoing features may be more fully understood from the following description of the drawings. The drawings aid in explaining and understanding the disclosed technology. Since it is often impractical or impossible to illustrate and describe every possible embodiment, the provided figures depict one or more illustrative embodiments. Accordingly, the figures are not intended to limit the scope of the broad concepts, systems and techniques described herein. Like numbers in the figures denote like elements.
Described herein are techniques to form a passivation stack having an etch stop layer. The techniques described herein enable for a passivation stack that is thicker than a top of metallization layer that reduces or eliminates passivation stack cracking. Without an etch stop layer, the variation in the passivation stack thickness may be excessive, thus the pad etch may have endpoint issues, which may require excessive over etch to ensure that the pads are clear of oxide and other materials but results in scrapping die lots due to poor endpoint detection. The techniques described herein minimize pad etch time and keep the passivation stack thickness over the pads consistent.
Other advantages of the techniques described herein include but are limited to: reducing the amount of glass layers that are deposited because the etch stop layer is part of the passivation stack, reducing thickness variations across a die, reducing polishing and etching time during processing, using similar processing techniques as pad etching processes, and so forth.
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In one example, a thickness of a passivation stack (i.e., the glass layer 20, glass layer 30, the etch stop layer 40 and the glass layer 50) above the metallization layer 10 prior to etching is between 1.5 to 2.5 times the thickness of the metallization layer 10. For example, if the metallization layer 10 is 2.5 microns thick, the passivation stack thickness above the metallization layer 10 prior to etching is about 3.8 microns.
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Process 200 deposits a first glass layer on a metallization layer (202). For example, the glass layer 20 is deposited on the metallization layer 10 using plasma enhanced chemical vapor deposition between 350° C. and 400° C., as depicted in
Process 200 deposits a second glass layer on the first glass layer (206). For example, the glass layer 30 is deposited on the glass layer 20 using high density plasma, as depicted in
Process 200 deposits an etch stop layer on the second glass layer (212). For example, the etch stop layer 40 is deposited on the glass layer 30 using plasma enhanced chemical vapor deposition, as depicted in
Process 200 deposits a third glass layer on the silicon nitride layer (218). For example, the glass layer 50 is deposited on the etch stop layer 40 using plasma enhanced chemical vapor deposition, as depicted in
Process 200 polishes the third glass layer down to the first silicon nitride layer (222). For example, the glass layer 50 is polished down to at least the surface of the etch stop layer 40 using a CMP process, as depicted in
Process 200 may deposit a silicon nitride layer on the etch stop layer and the remaining glass layer (228). For example, the silicon nitride layer 60 is deposited on the etch stop layer 40 and the remaining glass layer 50 using plasma enhanced chemical vapor deposition, as depicted in
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The processes described herein are not limited to the specific examples described. For example, the process 200 is not limited to the specific processing order of
Having described embodiments, which serve to illustrate various concepts, structures, and techniques, which are the subject of this patent, it will now become apparent to those of ordinary skill in the art that other embodiments incorporating these concepts, structures and techniques may be used.
Elements of different embodiments described herein may be combined to form other embodiments not specifically set forth above. Various elements, which are described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. Other embodiments not specifically described herein are also within the scope of the following claims.
