Claims
- 1. A memory cell, comprising:a first multi-doped region, wherein said first multi-doped region is formed by a plurality of doped regions; a second multi-doped region, wherein said second multi-doped region is formed by a plurality of doped regions; a first gate which is coupled to said first multi-doped region; a second gate which is coupled to both said first multi-doped region and said second multi-doped region; a third gate which is coupled to both said first multi-doped region and said second multi-doped region, wherein the interface of said second gate and said first multi-doped region is located between the interface of said first gate and said first multi-doped region and the interface of said third gate and said first multi-doped region; and a fourth gate which is coupled to said second multi-doped region, the voltage of said fourth gate being independent of the voltage of said first gate, wherein the interface of said third gate and said second multi-doped region is located between the interface of said second gate and said second multi-doped region and the interface of said fourth gate and said second multi-doped region.
- 2. The memory cell of claim 1, wherein said first multi-doped region comprises a N-type doped region and a P-type doped region.
- 3. The memory cell of claim 1, wherein said second multi-doped region comprises a N-type doped region and a P-type doped region.
Parent Case Info
This is a division of U.S. patent application Ser. No. 09/695,161, filed Oct. 24, 2000 now U.S. Pat. No. 6,366,493.
US Referenced Citations (5)