Patent Application
20140152715
1. Field of the Invention
The present invention relates generally to frame rate conversion, and more particularly to, a frame rate converter, a timing controller, a processing apparatus, and related method for a low-latency frame rate conversion.
2. Description of the Prior Art
Liquid crystal-based displays, such as liquid crystal based display (LCD) or Liquid crystal on silicon (LCoS) are notoriously known to have motion blur due to the slow response and sample-hold characteristics of liquid crystals. To alleviate the motion blur, improving the LC response is one of possible solutions. However, if the response time is shortened, there must be more frames generated to refresh the display device. Frame rate conversion is a technique used to generate more insertion frames. These additional insertion frames will be inserted between original consecutive frames.
There are several common ways of generating insertion frames, such as motion compensation/motion estimation, black frame insertion, and frame duplication. In the case of frame duplication, a duplication of a previous frame will be created and then inserted between the previous frame and a following frame. Due to duplication of image data of the previous frame, frame delay is therefore generated.
With this in mind, it is one objective of the present invention to provide a frame rate conversion technique which causes less frame delay compared to the conventional art. In the present invention, color sequential displaying method is used in conjunction with an image data rearrangement technique.
A first aspect of embodiments of the present invention provides a frame rate converter. The frame rate converter comprises: a receiving circuit, a frame buffer and a first multiplexer. The receiving circuit is utilized for receiving an input image data and accordingly outputting an output image data, the input image data having a plurality of data segments with information of a plurality of color components of pixels of a frame, respectively, wherein each of the data segments includes information of a same color component only. The frame buffer is coupled to the receiving circuit and utilized for storing the output image data. The first multiplexer is coupled to the frame buffer and the receiving circuit, and utilized for selecting one of the output image data outputted from the receiving circuit and the output image data buffered in the frame buffer as an output of the frame rate converter. Additionally, the first multiplexer outputs the output image data buffered in the frame buffer at least once after outputting the output image data outputted from the receiving circuit to generate at least one duplication of the frame.
A second aspect of embodiments of the present invention provides a frame rate converter for stereoscopic display. The frame rate converter comprises a receiving circuit and a buffer module. The receiving circuit is utilized for receiving a left-view input image data and a right-view input image data, and accordingly outputting a left-view output image data and a right-view output image data, each of the left-view input image data and the right-view input image data comprising a plurality of data segments with information of a plurality of color components of pixels of an interleaved frame, respectively, wherein each of the data segments includes information of a same color component only. The buffer module comprises a first frame buffer and a second frame buffer. The first frame buffer is coupled to the receiving circuit, and utilized for storing the left-view output image data. The second frame buffer is coupled to the receiving circuit, and utilized for storing the right-view output image data. The first frame buffer outputs the left-view output image data buffered therein more than once, and the second frame buffer outputs the right-view output image data buffered therein more than once to generate at least one duplication of each interleaved frame.
A third aspect of embodiments of the present invention provides a timing controller. The timing controller comprises: a receiving circuit, a frame buffer, a first multiplexer and a backlight source controlling circuit. The receiving circuit is utilized for receiving an input image data and accordingly outputting an output image data, the input image data having a plurality of data segments with information of a plurality of color components of pixels of a frame, respectively, wherein each of the data segments includes information of a same color component only. The frame buffer is coupled to the receiving circuit, and utilized for storing the output image data. A first multiplexer is coupled to the frame buffer and the receiving circuit, and utilized for selecting one of the output image data outputted from the receiving circuit and the output image data buffered in the frame buffer as an output of the frame rate converter. The backlight source controlling circuit is utilized for controlling operating timing of a plurality of backlight sources in response to a plurality of color component identifiers respectively corresponding to each data segment. The first multiplexer outputs the output image data buffered in the frame buffer at least once after outputting the output image data outputted from the receiving circuit to generate at least one duplication of the frame.
A fourth aspect of embodiments of the present invention provides a timing controller for stereoscopic displaying. The timing controller comprises a receiving circuit, a buffer module and a backlight source controlling circuit. The receiving circuit is utilized for receiving a left-view input image data and a right-view input image data, and outputting a left-view output image data and a right-view output image data, each of the left-view input image data and the right-view input image data comprising a plurality of data segments with information of a plurality of color components of pixels of an interleaved frame, respectively, wherein each of the data segments includes information of a same color component only. The buffer module comprises a first frame buffer and a second frame buffer. The first frame buffer is coupled to the receiving circuit, and utilized for storing the left-view output image data. The second frame buffer is coupled to the receiving circuit, and utilized for storing the right-view output image data. The backlight source controlling circuit is utilized for controlling operating timing of a plurality of backlight sources in response to a plurality of color component identifiers respectively corresponding to each data segment. The first frame buffer outputs the left-view output image data buffered therein more than once, and the second frame buffer outputs the right-view output image data buffered therein more than once to generate at least one duplication of each interleaved frame.
A fifth aspect of embodiments of the present invention provides a method of rearranging image data. The method comprises: successively receiving data of a plurality of pixels of a frame, wherein data of each of the pixels includes information of a plurality color components; and rearranging the data of each of the pixels of the frame to generate a plurality of data segments, wherein the data segments include information of the color components of the pixels, respectively, and each of the data segments includes information of a same color component only.
A sixth aspect of embodiments of the present invention provides a processing apparatus of rearranging image data. The processing apparatus comprises: a receiving unit and a rearranging unit. The receiving unit is utilized for successively receiving data of a plurality of pixels of a frame, wherein data of each of the pixels includes information of a plurality color components. The rearranging unit is utilized for rearranging the data of each of the pixels of the frame to generate a plurality of data segments, wherein the data segments include information of the color components of the pixels, respectively, and each of the data segments includes information of a same color component only.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Certain terms are used throughout the following descriptions and claims to refer to particular system components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not differ in functionality. In the following discussion and in the claims, the terms “include”, “including”, “comprise”, and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” The terms “couple” and “coupled” are intended to mean either an indirect or a direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
In order to ameliorate the frame delay caused by the frame rate conversion, the present invention utilizes image data rearrangement method and color sequential displaying method. The illustration of the image data rearrangement method is shown
The method of rearranging the image data as shown in
Please refer to
The frame delay caused by the frame rate conversion can be ameliorated by using the inventive image data rearrangement method and the color sequential displaying method. The reason will be apparent from the following description and
Based on the abovementioned image data rearrangement method, the present invention further provides a frame rate converter. With reference to
At first, an image data comprising data segments A, B, and C is sequentially inputted (each time 24-bit long color code is inputted) to the frame converter 300, the first multiplexer 330 selects the output image OUT_IMG of the receiving circuit 310 as the output (i.e., Frame 1R), wherein the output image OUT_IMG is one of data segments A, B, and C. Also, the output image OUT_IMG is stored in the frame buffer 320. Once the output image OUT_IMG of the receiving circuit 310 has been completely sent to the display terminal. The frame buffer 320 then continues to store a next data segment (i.e., Frame 1G) and the first multiplexer 330 outputs data buffered in the frame buffer 320 to generate a duplication of the frame (i.e., Frame 1R′). Please note that the first multiplexer 330 may outputs the output image data OUT_IMG buffered in the frame buffer 320 more than once to generate more insertion frames.
In one embodiment, the receiving circuit 310 further comprises a plurality of gamma conversion units 312-316 and a second multiplexer 318. The gamma conversion units 312-316 perform gamma conversions on the data segments of the input image data IN_IMG. Each of gamma conversion units 312-316 will perform a gamma conversion corresponding to a specific color on the data segments A, B, and C. For example, the Red gamma conversion unit 312 will perform gamma conversion on the data segment A. The second multiplexer 318 is coupled to the gamma conversion units 312-316, and operates in response to a plurality of color component identifiers respectively corresponding to the data segments. Each data segment corresponds to a specific color component identifier. The second multiplexer 318 will multiplex outputs of the gamma conversion units 312-316 to generate the output image data OUT_IMG.
According to one exemplary embodiment, the present invention further provides a timing controller including the above-mentioned frame rate converter. With reference to
The present invention also provides a frame rate converter for stereoscopic display. With reference to
In this embodiment, the duplication of each interleaved frame (e.g. left-view image or right-view image) are performed by the first frame buffer 522 and the second frame buffer 524, respectively. The output of the receiving circuit 510 will not be directly provided to the stereoscopic display terminal 530, and it must be buffered in the first frame buffer 522 and the second frame buffer 524 at first. Then, the duplication of each interleaved frame is generated from the outputs of the first frame buffer 522 and the second frame buffer 524.
Similarly, the receiving circuit 510 comprises a plurality of gamma conversion units 512-516 and a multiplexer 518. The gamma conversion units 512-516 perform gamma conversions on the data segments of the input image data IN_IMG_L and IN_IMG_R. Each of gamma conversion units 512-516 will perform a gamma conversion corresponding to a specific color on the image data IN_IMG_L and IN_IMG_R. The multiplexer 518 is coupled to the gamma conversion units 512-516, and operates in response to a plurality of color component identifiers respectively corresponding to the image data IN_IMG_L and IN_IMG_R. The multiplexer 518 will multiplex outputs of the gamma conversion units 512-516 to generate the output image data OUT_IMG_L and OUT_IMG_R.
According to one exemplary embodiment, the present invention further provides a timing controller for a stereoscopic display, which includes the frame rate converter shown in
The methodologies described herein may be implemented by various means depending upon the application. For example, these methodologies may be implemented in hardware, firmware, software, or any combination thereof. For a hardware implementation, the processing units may be implemented within one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processor, electronic devices, other electronic units designed to perform the functions described herein, or a combination thereof. For a firmware and/or software implementation, the methodologies may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. Any machine-readable medium tangibly embodying instructions may be used in implementing the methodologies described herein. For example, software codes may be stored in a memory and executed by a processor unit. Memory may be implemented within the processor unit or external to the processor unit.
In conclusion, the present invention reduces the frame delay caused by the frame rate conversion in the conventional art. By rearranging the image data and utilizing a color-sequential display method, the frame rate can be improved without causing severe frame delay.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
