A portion of the disclosure of this patent document contains material, which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
The present application claims priority from the Chinese Invention Patent Application Nos. 202111168594.3 filed on Sep. 30, 2021, and the disclosure of which is incorporated herein by reference in its entirety.
The present invention is generally related to active matrix display devices. More particularly, the present invention is related to frame rate-convertible active matrix display devices based on digital driving signals.
There are always desires for display devices capable of displaying smooth and true color videos for various types of video contents and image sources. In general, an active matrix display includes pixels and each pixel includes a driver circuit comprising switching elements such as transistors and storage elements such as capacitor for actively addressing the pixel and maintaining the pixel state. Typically, the pixels are selected row by row by a gate driver through a plurality of scan lines and then each pixel at the selected row is controlled by a source driver through a corresponding data line to emit light for displaying an image.
Active matrix display devices may be driven with analog or digital driving signals. In the analogy approach, brightness of a pixel is controlled with analog signals such as voltage or current levels of the driving signal, whereas in the digital approach, brightness of a pixel is controlled with pulse width of the driving signal. The digital approach has been gaining popularity over the analogy approach as it can use digital video signals directly for pixel driving therefore requires relatively simple driver circuits and has less power consumption. It has also better luminance uniformity because the display quality is less sensitive to variances in current-voltage characteristics of the transistors in pixel driver circuits.
In the digital modulation approach, image frame for each pixel is divided into a number of sub-frames each corresponds to a bit in the digital image data to be displayed. The subframes may have different durations which are weighted according to positions of bits to be represented respectively and under a rule that the more significant bit the subframe represents the longer the subframe duration is.
For each sub-frame, each row of pixels is scanned for a scan time. Pixels of the scanned row are then controlled to emit at a fixed luminance (turned ON) or zero luminance (turned OFF) to represent a logical value of “1” or “0” respectively and hold the state over the subframe duration. As such, a gray level scale of 2k levels can be achieved by means of aggregation of a hold time over which the pixel is turned ON within each frame.
Conventionally, the scan lines are scanned sequentially in each subframes and the sub-frames are arranged sequentially in an ascending/descending order and repeated cyclically. However, in order to accomplish high display resolution or dynamic range, the scanning speed may not high enough such that the scanning cannot be completed before start of next frame. If the scan time of the present frame is longer than the period of a last subframe and overruns into the first subframe of the next frame, there are two scan lines in operation concurrently over the first subframe of the next frame.
Under a limited display capability, good balance between color depth and frame rate is required to achieve optimal display quality. For example, for a display device with a standard configuration of color depth of 24 bits at 60 Hz frame rate which is adequate for most general applications, it may be better to display fast moving objects at higher frame rates (e.g., 120 Hz) to avoid motion blur but a lower color depth (e.g., 12-bit) will be resulted. The reduction of color depth may cause inaccurate color presentation such as color banding in images. For example, when an image originally displayed at color depth of 8 bits per component as shown in
According to one aspect of the present invention, a dithering and directional modulation-based frame rate conversion apparatus is provided. The apparatus comprises: a directional delta modulation generator configured to receive a plurality of input color data representing a plurality of input color components of an input pixel color and generate a plurality of modulated data for the plurality of input color data respectively; and a plurality of dithering modules configured to perform K-bit dithering conversion on the plurality of input color data respectively to generate a plurality of output color data for representing a plurality of output color components of an output pixel color with a color depth of K bits per component, where K is an integer equal to or great than 1. Each of the dithering modules comprising: a residue line buffer configured to track a residual error in dithering conversion to generate a respective residual data; an adapter configured to receive a respective input color data, a respective modulated data from the directional delta modulation generator and the respective residual data, and adapt the respective input color data to generate a respective adapted color data by adding the respective input color data with the respective modulated data and the respective residual data; and a dithering engine configured to receive the respective adapted color data and compare the respective adapted color data against a (2K−1) number of dithering threshold values to generate a respective output color data with 2K possible color levels.
According to another aspect of the present invention, a dynamic motion detection method for detecting motion content in a video to be displayed by a display device is provided. The method comprises: detecting, by a dynamic motion detection apparatus, motion content of the video and generating, by the dynamic motion detection apparatus, a motion detection result; receiving, by a frame rate controller, the motion detection result; and generating, by the frame rate controller, a control signal for controlling a display color depth based on the motion detection result. The video is displayed with a lower color depth at a higher frame rate than a standard configuration of the display device if the motion detection result indicates that the video contains appreciable amount of motion content; and the video is displayed with a higher color depth at a lower frame rate than the standard configuration of the display device if the motion detection result indicates that the video is relatively static.
By applying directional modulation before performing K-bit dithering conversion on input color data to generate output color data with a color depth of K bits per component, the display device can support frame rates higher than its standard configuration without observable color depth degradation. As shown in
Embodiments of the invention are described in more details hereinafter with reference to the drawings, in which:
FIG.3 depicts a block diagram of a dithering and directional modulation-based frame rate conversion apparatus according to one embodiment of the present invention;
In the following description, methods for driving an active matrix display for frame-rate conversion and the display device for implementing the same are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the invention. Specific details may be omitted so as not to obscure the invention; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.
The timing controller 12 may comprise a dynamic motion detection apparatus 121 configured to detect motion content of a video and generate a motion detection signal (V_MD); a frame rate controller 122 configured to receive the motion detection result and the input color data, and generate a control signal (V_Ctrl) for controlling a display color depth, a dithering and directional modulation-based frame rate conversion apparatus 123 configured to receive the control signal and convert the input color data to the output color data based on directional modulation and dithering such that the video can be displayed without observable color depth degradation even if the display frame rate is higher than the standard configuration of the display device. The timing controller 12 may further comprise a frame buffer 124 connected to the frame rate controller 122 and configured to store color data.
In particular, if the motion detection result for the video indicating that the video contains appreciable amount of motion content, the display device will display the video with a lower color depth (e.g., 4 bits per color components) at a higher frame rate (e.g. 120 Hz) than a standard configuration of the display device. If the motion detection result indicating that is the video is relatively static, the display device will display the video with a higher color depth (e.g., 8 bits per color component) at a lower frame rate (e.g. 60 Hz) than the standard configuration of the display device.
FIG.3 depicts a block diagram of a dithering and directional modulation-based frame rate conversion apparatus 123 according to one embodiment of the present invention. Referring to
The directional delta modulation generator 310 may be configured to receive a plurality of input color data (R_In, G_In and B_In) representing RGB color components of an input pixel color, a plurality of synchronization signals (V_Sync) and a control signal (V_Ctrl); and generate a plurality of modulated data (R_Mod, G_Mod and B_Mod) for the plurality of input color data respectively.
Each dithering module 320 may comprise a respective residue line buffer 322 configured to track a residual error in dithering conversion and generate a respective residual data (R_Res/G_Res/B_Res); and a respective adapter (or adder) 321 configured to receive a respective input color data (R_In/G_In/B_In), a respective modulated data (R_Mod/G_Mod /B_Mod) from the directional delta modulation generator 310, and a respective residual data (R_Res/G_Res/B_Res) from a respective residue line buffer 322 to adapt the respective input color data to generate a respective adapted color data (R_AD/G_AD/B_AD) by adding the respective input color data with the respective modulated data and the respective residual data.
Each dithering module 320 may further comprise a dithering engine 323 configured to receive a respective adapted color data (R_AD/G_AD /B_AD) from a respective adapter and generate a respective output color data (R_Out/G_Out/B_Out).
Depending on the frame-rate conversion target, each dithering engine 323 may be configured to perform K-bit dithering to convert the respective adapted color data to an output color data for representing a color depth of K bits per component, where K is an integer equal to or great than 1 which may be selected by the control signal (V_ctrl) from the frame rate controller 122. In particular, the respective adapted color data is compared against (2K−1) dithering threshold values to generate a respective output color data with 2K possible output color levels.
As shown in
As shown in
A color space cube for representing the pixel color may be divided into a number of sub-color space cubes depending on the color depth to be displayed. For instance, in a RGB color space, with a color depth of K bits per component in each RGB direction, a color space cube may be divided into an 8K number of sub-color space cubes and there are K number of quantized color levels in each RGB direction. Accordingly, each sub-color space cube corresponds to a set of RGB color levels.
The directional delta modulation generator 310 may be further configured to determine a modulation direction by comparing each of the color components of the pixel color against a modulation threshold value and obtaining a flag value of modulation for each of the color components. For instance, if a color component of the pixel has a value equal to or greater than the modulation threshold value, the flag value of modulation for the color component is set as “1”, otherwise, the flag value of modulation for the color component is set as “0”.
Accordingly, the flag values of modulation for each of the color components may be used to construct a modulation direction unit vector Um (xm, ym, zm) in the RGB color space to represent the modulation direction, where xm, ym, and zm are RGB components of the unit vector respectively. Each of the RGB components xm, ym, and zm of the modulation direction unit vector Um may have a binary value (“1” or “0”) determined by comparing RGB component values of the pixel color against with the modulation threshold value respectively. For instance, if the R component value of the pixel color is equal to or greater than the modulation threshold value, xm is set to “1”, otherwise xm is set to be “0”. In other words, whether delta modulation is applied in a color component (direction) in the color space depends on whether the component value of the pixel color in that color component (direction) is equal to or greater than the modulation threshold value.
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The directional delta modulation generator 310 may be further configured to apply a delta modulation based on the determined flag value to each of the color components of the pixel to obtain a modulated data for the color component.
The delta modulation may be performed across a sequence of image frames over a modulation cycle using a sequence of N delta modulation values to obtain N modulated data for each of the color components. Within the modulation cycle, an ith modulated data for the color component obtained in the ith frame may be given by:
Xmi=Xoi+di, for i=1, 2, . . . , N,
where Xmi is the ith modulated data obtained in the ith frame, Xoi is the original value of the input color data in the ith frame, di is the delta modulation value used in the ith frame which may have a positive or negative value, and N is the total number of frames within a modulation cycle.
Preferably, the sequence of N delta modulation values di, may be selected to have a sum equal to zero, that is, Σi=1Ndi=0, in order to apply the delta modulation across the frames in a balanced manner.
Within the modulation cycle, the dithering engine 323 may be further configured to determine a N number of color levels for the color component of the pixel based on the Nmodulated data obtained across the N number of frames respectively.
The ith color level for the color component based on the modulated data Xmi obtained in the ith frame may be determined with an algorithm given by:
where Ci is the ith color level obtained in the ith image frame, Lk is the kth color levels defined in the color space with the color depth of K bits per component to be displayed.
The dithering engine 323 may be further configured to average the N color levels for the color components of the pixel determined across the sequence of frames over the modulation cycle to obtain an average display color value Cavg, which is given by:
and set the average display color value as the output color level.
and
which is represented as a dot within the sub-color space squares corresponding to Lk. By way of example, the delta modulation values (di) used in the modulation cycle are set as: d1=0, d2=−δ, d3=δ, d4=0, d5=−2δ, and d6=2δ, where δ is a predefined delta value.
Referring to
and less than Lk. That is,
The color levels of the pixel color component in the 6 frames are determined as: C1=Lk, C2=Lk−1, C3=Lk, C4=Lk, C5=Lk−1, and C6=Lk. The average display color value Cavg is equal to (2Lk−1+4Lk)/6, which is a color level between Lk−1and Lk.
Referring to
Referring to
That is,
The color levels of the pixel color component in the 6 frames are determined as: C1=Lk, C2=Lk, C3=Lk+1, C4=Lk, C5=Lk, and C6=Lk+1As a result, the average display color value Cavg is equal to (4Lk+2Lk+1)/6, which is a color level value between Lk and Lk+1.
It can be observed from
and less than Lk, has an average display color value between Lk−1and Lk over the modulation cycle; the color component of the pixel for the case in
has an average display color value between Lk and Lk+1 over the modulation cycle. In other words, the display image is smoothened by applying the directional modulation therefore the observable degradation of color depth due to frame rate conversion can be eliminated.
In some embodiments, with the dithering and directional modulation-based frame rate conversion apparatus, an input image source having 60 Hz frame rate at color depth of 8 bits per component may be converted to an output image source with color depth of 2 bits per component displayed at 240 Hz frame rate, color depth of 3 bits per component displayed at 180 Hz frame rate or color depth of 4 bits per component displayed at 120 Hz frame rate.
The dithering and directional modulation-based frame rate conversion apparatus can be configured to support conversion of image sources (say, from a computer graphic card) having various frame rates. For example, an input image source having 60 Hz frame rate at color depth of 8 bits per component may be converted to an output image source with color depth of 2 bits per component displayed at 240 Hz frame rate, color depth of 3 bits per component displayed at 180 Hz frame rate or color depth of 4 bits per component displayed at 120 Hz frame rate.
In some embodiments, the output image source may have a mix of different display formats of frame rates including but not limited to, 240 Hz, 200 Hz, 180 Hz, 150 Hz, 120 Hz, 100 Hz, 80 Hz and 60 Hz.
Referring to
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Referring to
In some embodiments, the vote may have a first voting value for the element if the comparison result is that the element is equal to or lower than the first voting threshold value; a second voting value which is higher than the first voting value for the element if the comparison result is that the element is higher than the first voting threshold value and lower than the second voting threshold value; or a third voting value which is higher than the second voting value for the element if the comparison result is that the element is equal to or higher than the second voting threshold value.
The process of dynamic motion detection may further include: i) calculating, by a majority vote logic unit 940, a sum of the votes generated for all elements of the array of brightness differences; j) determining, by the majority vote logic unit 940, the motion detection result by comparing the calculated sum of the votes with one or more motion detection threshold values; and k) generating, by the majority vote logic unit 940, a motion detection signal (V_MD) to the frame rate controller 122 based on the motion detection result.
In some embodiments, if the calculated sum is equal to or higher than a motion detection threshold value, the motion detection result may be determined as that the video includes appreciable amount of motion contents. Based on the determined motion detection result, the frame rate controller 122 may determine to display the video with a lower color depth at a higher frame rate than the standard configuration of the display device (e.g., with a color depth of 4 bits per color components and at a frame rate of 120 Hz). If the calculated sum is smaller than the motion detection threshold value, the motion detection result may be determined as that the video is relatively static. Based on the determined motion detection result, the frame rate controller 122 may determine to display the video with a higher color depth at a lower frame rate than the standard configuration of the display device (e.g., with a color depth of 8 bits per color components and at a frame rate of 60 Hz).
A new round of dynamic motion detection may be performed by: taking a previous second frame in a previous round of motion detection as a new first frame for the new round of motion detection; calculating brightness values of a new second frame which is ΔF frames after the new first frame; overwriting the brightness data array which has stored brightness values of a previous first frame in the previous round of motion detection with the calculated brightness values for the new second frame; and repeating the above steps f) to k). As there is no need to calculate the brightness values for the new first frame, the computation time for new round of motion detection can be greatly reduced.
Referring to
Referring to
Referring to
For each region, a vote is generated to have: a first voting value “0” if the corresponding brightness difference is equal to or lower than the first voting threshold value 5%, a second voting value “1” if the corresponding brightness difference is higher than the first voting threshold value 5% and lower than the second voting threshold value 20%, or a third voting value “2” if the corresponding brightness difference is equal to or higher than the second voting threshold value 20%. Based on a sum calculated for all of the generated votes, a second motion detection result is determined, and a motion detection signal is generated and transmitted to the frame rate controller 122. For example, if the calculated sum is equal to or greater than a motion detection threshold value “100”, based on the second motion detection result the frame rate controller may determine a display output format with a color depth of 4 bits per color component at a frame rate of 120 Hz.
Referring to
The embodiments disclosed herein may be implemented using general purpose or specialized computing devices, computer processors, or electronic circuitries including but not limited to digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA), and other programmable logic devices configured or programmed according to the teachings of the present disclosure. Computer instructions or software codes running in the general purpose or specialized computing devices, computer processors, or programmable logic devices can readily be prepared by practitioners skilled in the software or electronic art based on the teachings of the present disclosure. In some embodiments, the present invention includes computer storage media having computer instructions or software codes stored therein which can be used to program computers or microprocessors to perform any of the processes of the present invention. The storage media can include, but are not limited to ROMs, RAMs, flash memory devices, or any type of media or devices suitable for storing instructions, codes, and/or data.
The embodiments were chosen and described in order to best explain the principles of the invention and its working principle and practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations will be apparent to the practitioner skilled in the art.
Number | Date | Country | Kind |
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202111168594.3 | Sep 2021 | CN | national |
Number | Name | Date | Kind |
---|---|---|---|
10210788 | Su | Feb 2019 | B2 |
20060139696 | Yamamoto | Jun 2006 | A1 |
20070116367 | Yamamoto | May 2007 | A1 |
20150235587 | Su | Aug 2015 | A1 |
20180254020 | Buckley | Sep 2018 | A1 |
20190073754 | Chen | Mar 2019 | A1 |