Patent Application
20220285813
As is known in the art, conventional frequency selective limiters (FSLs) have been limited in instantaneous bandwidth and maximum operating frequency. Conventional FSLs are made using Yttrium Iron Garnet (YIG) grown on Gadolinium Gallium Garnet (GGG) using Liquid Phase Epitaxy. In prior art FSLs, a YIG film layer grown by liquid phase epitaxy on a GGG substrate is used to realize devices capable of functions like RF filtering, frequency selective limiting, and time delay over limited frequency ranges (bandwidths).
Some known FSLs are magnetostatic surface wave (MSSW) devices. The operating frequency of the MSSW FSL is limited by the dispersion characteristics of magnetic spinwaves, including MSSWs and half-frequency (w/2) spinwaves. The YIG film is attached to the GGG, so only one side is free to be placed adjacent an MSSW transducer.
The theory of MSSW transducers and devices is well known to those skilled in the art.
Adam's publication titled “Microwave Magnetostatic Delay Devices Based on Yttrium Iron Garnet” Proceedings of the IEEE, Vol. 64, No. 5 May 1976 and Patterson, O'Keefe and Adam's U.S. Pat. No. 4,199,737 “Magnetostatic Wave Device,” which is incorporated herein by reference, describes the MSSW transduction and propagation, including the theoretical description of physics, but does not describe an FSL. The realization of practical circuit topologies that enable the enhanced bandwidth of MSSW transducers for FSL devices is difficult.
Adam describes a MSSW Signal-to-Noise enhancer device with improved bandwidth in “A SLOT-LINE MSW SIGNAL-TO-NOISE ENHANCER” 1794 IEEE TRANSACTIONS ON MAGNETICS, VOL. MAG-21, NO. 5, SEPTEMBER 1985, building on prior art U.S. Pat. No. 4,283,692A “Magnetostatic wave Signal-to-Noise enhancer,” both of which are incorporated herein by reference. However, the slot-line embodiment requires the use of non-trivial microstrip to slot-line converters, and does not apply to FSLs, but rather apply to signal-to-noise enhancers.
Another way to increase the bandwidth of an MSSW device is to reduce the magneto-crystalline anisotropy of the magnetic film by growing the film on various crystallographic planes of the seed crystal. This allows for achieving lower operating frequency, but not higher. This is described in U.S. Pat. No. 6,232,850B1 “Magnetostatic wave device with specified angles relating the transducer, magnetic thin film, and bias magnetic field,” which is incorporated herein by reference, but does not apply to FSLs.
Adam describes a MSSW FSL in U.S. Pat. No. 6,998,929 B1 “Low Threshold Power Frequency Selective Limiter for GPS,” which is incorporated herein by reference, that uses a YIG film on a GGG substrate, placed film side down on top of a pair of short circuited microstrip transducers which were fabricated on a dielectric substrate. Adam '929 is based on prior art by Murphy and Littlepage in U.S. Pat. No. 5,955,987 “Hybrid Radio Frequency System With Distribution Anti-Jam Capabilities for Navigation Use,” which are incorporated herein by reference.
The concepts, systems, circuits and devices described herein relate to frequency selective limiters (FSL) capable of operating over a wide frequency range and which may be implemented using microstrip transducers, for example. In accordance with the concepts, systems, circuits and techniques described herein, described are circuit topologies that result in enhanced bandwidths of FSL devices. In embodiments, FSL devices are magnetostatic surface wave (MSSW) type devices.
A frequency selective limiter (FSL) refers to a nonlinear passive device that attenuates radio frequency (RF) signals provided to an input thereof having a power level which is above a predetermined threshold power level. Hence, FSLs are said to limit the amount of power of an RF signal. RF Signals having a power level below the predetermined threshold power, on the other hand, propagate from the FSL input port to the FSL output port substantially unattenuated.
One feature of an FSL device is the frequency selective nature of the high-power limiting. Specifically, an FSL has a characteristic in which lower power signals (i.e., signals having a power level below the threshold power lever) close in frequency to the limited signals are substantially unaffected (i.e., the FSL does not substantially attenuate such signals).
In embodiments, described is the use of a free-standing YIG crystal. For the case of YIG grown using liquid phase epitaxy (LPE), the YIG crystal is grown over a GGG substrate and is then subsequently separated from the substrate to provide a free-standing YIG crystal film. As used herein, a free-standing YIG film refers to a film that has been separated from a substrate used to form the YIG film.
In embodiments, the YIG film is initially deposited (e.g. using LPE) or otherwise provided over a GGG substrate. The GGG substrate can be removed to provide a free-standing YIG crystal film. The YIG may be polished to provide desired surface characteristics. In some embodiments, the free-standing YIG crystal can be bonded to an RF ground plane. Wirebonds may be disposed across the YIG from input to ground and from output to ground. This approach results in a very compact and low cost FLS.
In embodiments, the free YIG crystal can be bonded directly to a ground plane in an integrated circuit (IC) package, such as a quad-flat no lead (QFN) semiconductor IC package. Wire bonds can be used to form the transducers inside the IC package.
By using a thin (e.g. 100 microns or less), free-standing YIG film, the device can be provided in a novel Type B configuration (see, e.g.,
One advantage of the described concepts, structures and techniques over prior art approaches for increasing the maximum frequency of FSLs is that the described concepts, structures and techniques require no exotic circuit types or materials. The separation of the GGG substrate from the YIG film facilitates placement of one surface of the YIG film on a conductive plane, while also allowing conventional transducer design techniques to be employed on the opposing surface of the YIG film.
In one aspect, a frequency selective limiter (FSL) device comprises: a free-standing Yttrium Iron Garnet (YIG) film having first and second opposing surfaces; a metal layer disposed on a first one of the first and second opposing surfaces of the YIG film to provide the YIG film with a metalized surface; and a first transducer disposed on a second one of the first and second surfaces of the YIG film.
An FSL device can further include one or more of the following features: the metal layer comprises an RF ground plane, the YIG film has a thickness in a range of about 50 to about 500 microns, the FSL comprises a Type A MSSW FSL device, the FSL comprises a Type B MSSW FSL device, the FSL device comprises a MSSW device, wherein the first transducer has a first end coupled to the metalized surface of the YIG film; and, further including a second transducer disposed on the second one of the first and second surfaces of the YIG film, the second transducer having a first end coupled to the metalized surface of the YIG film, wherein the first and second transducers are configured to launch magnetostatic surface wave (MSSWs) on the first and second surfaces of the YIG film, the first and second transducers comprise microstrip transducers, the first and second transducers comprise stripline transducers, the first and second transducers comprises coplanar waveguide (CPW) transducers, the first and second transducers comprise wirebonds, the metal layer covers an entirety of the first one of the surfaces of the YIG film, the MSSW FSL device is provided as a IC package, the IC package comprises a QFN type package, and/or the IC package comprise conductive vias to electrically couple the first and second transducers to input/output feed circuits.
In another aspect, a method of fabricating an FSL device comprises: depositing at least one transducer on a first side of a YIG film on a GGG wafer; singulating the wafer into individual devices; removing the GGG from a second surface of the YIG film to provide a free-standing YIG film with a free YIG surface; polishing the free YIG surface; disposing an electrically conductive material on the free YIG surface; and electrically coupling the at least one transducers to the electrically conductive material and to input/output feed circuits.
A method can further include growing the YIG film using Liquid Phase Epitaxy on both sides of the GGG wafer and wherein removing the GGG from the surface of the wafer comprises removing a layer of YIG film and removing the GGG, polishing the free YIG surface comprises polishing Chemical Mechanical Polishing (CMP) the YIG surface with colloidal silica nanoparticles to restore the free YIG surface to an optical polish, disposing the electrically conductive material on the free YIG surface comprises at least one of: sputtering a conductor onto the free YIG surface; and/or adhering the free YIG surface to a surface of a metal ground, before the removal of the GGG layer from the YIG film, covering the free surface of the YIG film with the electrically conductive material, the FSL device comprises a Type A MSSW FSL device, the FSL device comprises a Type B MSSW FSL device, after the GGG is removed and the YIG is polished, disposing the YIG film directly on a pair of Type A transducers, providing interconnects to connect to an RF ground plane, fabricating the FSL device without any metal deposition or processing on the YIG film, the YIG film is bonded directly to a ground plane in a semiconductor IC package and wire bonds are used to form the transducers inside the IC package, and/or removing the GGG comprises removing the GGG via a lapping procedure.
The manner and process of making and using the disclosed embodiments may be appreciated by reference to the drawings, in which:
As described more fully below, disposing the free-standing YIG 102 on the metal conductive layer 108 increases the upper cutoff frequency and increases the device bandwidth, as compared to conventional FSL devices having a YIG film on a GGG substrate.
In embodiments, the first and second transducers 210, 212 are electrically coupled to the RF ground plane 208 by coupling one end of each transducer to the ground plane, e.g. via a grounding structure, a wire bond, an electrically conductive via, or using any other technique well-known to those of ordinary skill in the art. In the illustrated embodiment, a first end 214 of the first transducer 210 is coupled to the ground plane 208 at a first location on the ground plane and a first end 216 of the second transducer 212 is coupled to the ground plane at a second location. In example embodiments, the grounded ends 214, 216 of the first and second transducers are located at opposite sides of the YIG film 202.
In the illustrated embodiment, a DC biasing field circuit 218 is configured to apply a DC biasing field (e.g., a DC H field, as shown) in a plane parallel to a plane in which the YIG film lies. A variety of suitable DC bias circuits 218 can be used to meet the needs of a particular application.
The structure of
It is understood that amount and geometry of the further conductive material 309 on the upper surface 304b of the YIG film 302 can vary to the meet the needs of a particular application. For example, the number and width of strips of conductive material 309 can vary to cover a selected area of the YIG film. In some embodiments, the conductive material 309 is symmetrical with respect to an axis centered on a midpoint of a side of the YIG film. In other embodiments, the conductive material 309 is not symmetrical.
It is understood that the thickness of the GGG, the number, depth, and geometry of the grooves in the GGG, the thickness of the YIG film, the type of transducer, etc., can vary to meet the needs of a particular application without departing from the scope of the invention as claimed.
The illustrative plot in
ω2=√{square root over (γ(Hinternal[Hinternal+4πM]))}
ω3=γ(Hinternal+2πM)
ω3,metal=γ(Hinternal+4πM)
ψ4=2γ(Hinternal)
γ=2.8 MHz/Oersted
4πM=1780 Gauss
When the surface of the YIG film 202 (
It will be appreciated that this makes launching of MSSWs in this YIG-metal condition using conventional YIG on GGG difficult, because the only free YIG surface must be completely covered in metal, which means only certain types of excitation transducers can be used, such as slot line, or co-planar waveguide (CP).
In some embodiments, a YIG film may be grown on a surface of a substrate (e.g. a GGG substrate) using Liquid Phase Epitaxy and subsequently separated from the substrate and coupled to a surface of the RF ground plane.
Ideally, all of the GGG is removed from the YIG layer, however, there may be residual GGG. In embodiments, suitable techniques for stock removal of 500 microns of GGG (typical GGG wafer thickness) include fixed and loose abrasive lapping using grinding media such as Silicon Carbide, Alumina, Boron Carbide on a rotating iron lapping plate. After the GGG is removed using lapping, polishing may be done with loose abrasive on special polishing pads. In some embodiments, a last polishing may be done using chemical mechanical polishing (CMP). In embodiments, such polishing may be accomplished, for example, via a Chemical Mechanical Polishing (CMP) process (e.g. a CMP with fine colloidal silica nanoparticles may be used). Such a polishing process restores the now free YIG surface to an optical polish. Once the back side of the YIG is smoothed to within a desired range of roughness, the surface can be either sputtered with a conductor, or the bare YIG surface can be simply glued to a metal ground as part of an MSSW FSL device. In embodiments, the YIG material may be smoothed to a surface roughness in the range of 0-1000 nm peak-to-peak (pk-pk) and preferably to a surface roughness in the range of 0-500 nm pk-pk and even more preferably to a surface roughness in a surface roughness in the range of 0-10 nm pk-pk.
The transducers fabricated on the exposed (or “top”) surface of the YIG can be coupled to input/output feed circuits. Such coupling may be accomplished, for example, using wire bonds. Other techniques may also be used.
Additional features may be fabricated or otherwise provided onto an exposed surface of a YIG film. Such additional features may be provided either before or after separation of the YIG film from the GGG wafer (e.g. before or after the removal of the GGG layer from the YIG film). Such additional features include, but are not limited to, electrically conductive vias to allow for the use of surface mountable technology (SMT) directly on the YIG crystal to connect the top-side transducers to input and output feed networks without the use of wirebonds.
Materials capable of absorbing or reflecting MSSWs known to those skilled in the art can be deposited or otherwise provided on the free side of a YIG film (either before or after the removal of the GGG layer from the YIG film).
In some embodiments, before removing the GGG, the YIG surface could be covered with metal. Once the GGG is removed and the YIG is polished, it can be laid directly on a pair of Type A transducers and coupled to the transducers. Wire bonds or other interconnect technology (Flip Chip, SMT) can be used to connect the upper metal covered surface of the YIG to a RF ground plane.
In some embodiments, MSSW FSLs can be fabricated without any metal deposition or processing on the YIG. The GGG can be removed as described previously, and the YIG polished. The free YIG crystal can be bonded to a RF ground plane and wirebonds stretching across the YIG from input to ground and from output to ground. This results in a very compact and low cost design.
The free YIG crystal can be coupled to a ground plane (e.g. directly or indirectly coupled to the RF ground plane in a semiconductor IC package (e.g. a quad-flat no lead (QFN) semiconductor IC package) and wire bonds or other electrical connections can be provided to form the transducers inside the IC package.
Various embodiments of the concepts systems and techniques are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of the described concepts. It is noted that various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to element or structure “A” over element or structure “B” include situations in which one or more intermediate elements or structures (e.g., element “C”) is between element “A” and element “B” regardless of whether the characteristics and functionalities of element “A” and element “B” are substantially changed by the intermediate element(s).
The following definitions and abbreviations are to be used for the interpretation of the claims and the specification.
As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such method, article, or apparatus.
Additionally, the term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms “one or more” and “one or more” are understood to include any integer number greater than or equal to one, i.e. one, two, three, four, etc. The terms “a plurality” are understood to include any integer number greater than or equal to two, i.e. two, three, four, five, etc. The term “connection” can include an indirect “connection” and a direct “connection”.
References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” or variants of such phrases indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment can include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
Furthermore, it should be appreciated that relative, directional or reference terms (e.g. such as “above,” “below,” “left,” “right,” “top,” “bottom,” “vertical,” “horizontal,” “front,” “back,” “rearward,” “forward,” etc.) and derivatives thereof are used only to promote clarity in the description of the figures. Such terms are not intended as, and should not be construed as, limiting. Such terms may simply be used to facilitate discussion of the drawings and may be used, where applicable, to promote clarity of description when dealing with relative relationships, particularly with respect to the illustrated embodiments. Such terms are not, however, intended to imply absolute relationships, positions, and/or orientations. For example, with respect to an object or structure, an “upper” surface can become a “lower” surface simply by turning the object over. Nevertheless, it is still the same surface and the object remains the same. Also, as used herein, “and/or” means “and” or “or”, as well as “and” and “or.” Moreover, all patent and non-patent literature cited herein is hereby incorporated by references in their entirety.
The terms “disposed over,” “overlying,” “atop,” “on top,” “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, where intervening elements or structures (such as an interface structure) may or may not be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary elements or structures between the interface of the two elements.
Having described exemplary embodiments, it will now become apparent to one of ordinary skill in the art that other embodiments incorporating their concepts may also be used. The embodiments contained herein should not be limited to disclosed embodiments but rather should be limited only by the spirit and scope of the appended claims. All publications and references cited herein are expressly incorporated herein by reference in their entirety.
Elements of different embodiments described herein may be combined to form other embodiments not specifically set forth above. Various elements, which are described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. Other embodiments not specifically described herein are also within the scope of the following claims.
This application is a continuation of co-pending application Ser. No. 16/871,553 filed May 11, 2020, now U.S. Pat. No. 11,349,185 issued May 31, 2022, which claims the benefit of U.S. Provisional Patent Application No. 62/846,103, filed on May 10, 2019, which is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 62846103 | May 2019 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16871553 | May 2020 | US |
| Child | 17804151 | US |
