Patent Application
20190272936
Embodiments of the present disclosure relate to power management solutions, and in particular to methods and apparatuses that include embedded magnetic cores for use in inductors.
Efficient power management is crucial for many integrated circuit (IC) technologies, especially for high end server devices. Currently, voltage regulation in some ICs may be implemented with embedded voltage regulators. Such embedded voltage regulators often use air coil inductors (ACIs) formed by plating through hole walls with copper. However, ACIs may not provide the desired inductance. In order to increase the inductance, more ACIs may be formed in series. This increases the overall footprint of the voltage regulators. Additional solutions for increasing the inductances of ACIs have been proposed. For example, a magnetic core material may be positioned inside and around the coil.
However, the introduction of magnetic materials results in disruptions to currently used manufacturing processes. The magnetic materials leach and negatively affect chemistries used in the processing of IC substrates. For example, exposed magnetic materials may result in bath contamination during desmear, electroless copper plating, and subtractive etching processes.
Described herein are systems with fully embedded magnetic materials on IC substrates and methods of forming such systems. More particularly, embodiments include inductors with fully embedded magnetic cores and methods of forming such devices. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.
As noted above, the inclusion of magnetic materials in the manufacture of IC devices is currently problematic due to the leaching of magnetic materials (e.g., iron, alloys containing iron, and other ferromagnetic particles or elements) into processing baths. Accordingly, it is presently not feasible to integrate components, such as inductors, that benefit from the use of magnetic materials into IC substrates. However, embodiments described herein provide processing methods that allow for the integration of magnetic materials with currently available processing techniques. Particularly, embodiments include fully embedding magnetic materials so that the magnetic materials are not exposed to processing environments where the leaching of magnetic materials is detrimental. For example, embodiments include embedding the magnetic materials so that the magnetic materials are not exposed to processing environments that have chemistries that may be negatively altered by leached magnetic materials, such as electroless baths, and subtractive etching baths. Since the magnetic material is isolated from such environments, there is no need to redesign the chemistries of processing baths or provide dedicated processing baths to handle the magnetic materials. Furthermore, isolating the magnetic material allows for subsequent changes to the magnetic material to be made without needing to adjust the chemistries of processing environments. This allows for quicker design times and reduces the cost of development. In embodiments, the magnetic material always interfaces with an organic resin material instead of copper surfaces. This provides better reliability in terms of interface delamination and blistering.
In the particular embodiment of inductors that utilize fully embedded magnetic materials, it is to be appreciated that the inductors may have increased inductance relative to ACIs described above. As such, fewer turns are needed to provide a desired inductance relative to ACIs. Inductors with fully embedded magnetic cores, therefore, provide more efficient use of substrate area. Additionally, the plated through-hole pitch at the inductor area may be reduced compared to inductor structures that use a co-axial plated through-hole structure (i.e., forming a magnetic material around the plated through-hole in a co-axial structure). In co-axial plated through-hole structures, the pitch needs to be increased to accommodate for both the plated through-hole and the surrounding magnetic material. For example, the pitch needed to accommodate plated through-holes in co-axial arrangements may be 450 μm, and the pitch needed for plated through-holes described in embodiments herein may be 362.5 μm since the plated through-holes described herein may not be sheathed by the magnetic material.
In an embodiment, the plated through-holes in the inductor region may be the substantially similar (e.g., same pitch, geometry, and the like) as plated through-holes in other regions of the IC substrate. Additionally, the use of plated through-holes in the inductor region that are substantially similar to plated through-holes in the other regions of the substrate allow for a single set of drill bits to be used. This eliminates the cost of designing unique sets of drill bits specifically for the inductor region.
Referring now to
In the illustrated embodiment, the multi-phase voltage regulator 100 includes eight single turn inductors 110. It is to be appreciated that any number of inductors 110 may be included in the multi-phase voltage regulator 100. Additionally, while single turn inductors 110 are illustrated in
As illustrated in
In an embodiment, the inductors 110 (including traces 119, 120, 114, and plated through-holes 112) are formed around a magnetic core 115. The magnetic core 115 may pass entirely through the substrate core 105. Surfaces 117A and 117B of the magnetic core 115 may be substantially coplanar with surfaces of the substrate core 105. As used herein, “substantially coplanar” may refer to surfaces that are within +/−2 μm of being coplanar with each other. In an embodiment, surfaces 117A and 117B may be in contact with dielectric layers 108A and 108B, respectively. Dielectric layers 108A and 108B cover the magnetic core 115 during processing operations and isolate the magnetic core 115 from processing operations that may negatively interact with the magnetic material (as will be described in greater detail below). In an embodiment, dielectric layers 108A and 108B may be a prepreg material. The dielectric layers 108A and 108B may be laminated over surfaces of the substrate core 105. In an embodiment, the plated through-holes may also pass through the dielectric layers 108A and 108B.
The magnetic core 115 may also have sidewall surfaces 117C and 117B that are in contact with the substrate core 105. In an embodiment, the sidewall surfaces 117C and 117B may be substantially vertical. As used herein, “substantially vertical” may refer to surfaces that are within +/−5° from 90°. Additional embodiments may include sidewall surfaces 117C and 117B that are tapered surfaces.
The magnetic core 115 may be any suitable magnetic material. In an embodiment, the magnetic core 115 may be a dielectric material that includes magnetic particles. In one embodiment, the magnetic particles may include iron, alloys including iron, or any other elements or alloys that have magnetic properties. In an embodiment, the magnetic core 115 may have a relative permeability greater than 5. In an embodiment, the magnetic core 115 may have a relative permeability greater than 10.
In
Referring now to
The use of a plurality of magnetic cores 215 in each inductor 210 may allow for easier manufacturing. For example, the magnetic material used for the magnetic cores 215 may be a plugged into openings formed into the substrate core 205. Larger openings through the substrate core 205 may be relatively harder to form than smaller openings. As such, a plurality of smaller openings may be used to form a plurality of magnetic cores 215. In the illustrated embodiment, the magnetic cores 215 are cylindrical columns. However, embodiments are not limited to the shapes shown, and the magnetic cores 215 may have any desired cross-section.
Referring now to
Referring now to
Referring now to
Referring now to
Referring now to
Referring now to
Referring now to
In an embodiment, the magnetic core 615 may have a first surface 617A that is substantially coplanar with a first surface 606 of the substrate core 605, and the magnetic core 615 may have a second surface 617B that is substantially coplanar with a second surface 607 of the substrate core 605. Embodiments may also include a sidewall surfaces 617C and 617D that are in direct contact with the substrate core 605. The surfaces 617C and 617D may conform to the surfaces of the opening 650. As such, the profile of the surfaces 617C and 617D may match the profile of the opening 650 (i.e., vertical sidewalls, tapered sidewalls, etc.),
Referring now to
In the illustrated embodiment, conductive layers 661, 662 are disposed over the first and second dielectric layers 608A and 608B. In some embodiments the conductive layers 661 and 662 may be formed on the dielectric layers 608A and 608B prior to the dielectric layers 608A and 608B being disposed over the substrate core 605. In other embodiments, one or both of the conductive layers 608A and 608B may be omitted.
Referring now to
Referring now to
Referring now to
Referring now to
In other embodiments, there may be a plurality of magnetic cores formed within the core substrate. Such embodiments may be beneficial in order to improve the manufacturability of the embedded magnetic cores. Particularly, it may be easier to form smaller openings in the substrate core. A process flow for forming a plurality of fully embedded magnetic cores is shown in
Referring now to
In the illustrated embodiment three openings 750 are formed through the substrate core 705. In other embodiments, any number of openings 750 may be formed through the substrate core 705. In an embodiment, the openings 750 may have any cross-section, as seen from the top similar to the view illustrated in
In an embodiment, the plurality of openings 750 may be formed through the substrate core 705 with any suitable process. For example, the openings 750 may be formed with a mechanical drilling process, a laser drilling process, a wet or dry etching process, or the like. In an embodiment, the openings 750 may be cleaned with a desmear process. In the illustrated embodiment, the vertical sidewalls of the openings 750 are substantially vertical. However, it is to be appreciated that embodiments may also include sidewalls of the openings 750 that are tapered or otherwise shaped, depending on the process used to form the openings 750.
Referring now to
In an embodiment, the magnetic cores 715 may have a first surface 717A that is substantially coplanar with a first surface 706 of the substrate core 705, and the magnetic cores 715 may have a second surface 717B that is substantially coplanar with a second surface 707 of the substrate core 705. Embodiments may also include sidewall surfaces 717C and 717D that are in direct contact with the substrate core 705. The surfaces 717C and 717D may conform to the surfaces of the opening 750. As such, the profile of the surfaces 717C and 717D may match the profile of the opening 750 (i.e., vertical sidewalls, tapered sidewalls, etc.),
Referring now to
In the illustrated embodiment, conductive layers 761, 762 are disposed over the first and second dielectric layers 708A and 708B. In some embodiments, the conductive layers 761 and 762 may be formed on the dielectric layers 708A and 708B prior to the dielectric layers 708A and 708B being disposed over the substrate core 705. In other embodiments, one or both of the conductive layers 708A and 708B may be omitted.
Referring now to
Referring now to
Referring now to
In an embodiment, the lids 718 are conductive lids and may be formed with any deposition process. For example, the lids 718 may be formed with an electroless plating process. After the plating, a subtractive etching process may be implemented to define the pattern of the lids 718 and remove the conductive layers 761 and 762. In some embodiments, the subtractive etching process may also be utilized to form conductive traces along surfaces of the dielectric layers 708A and 708B used to connect the plated through-hole vias 712 in order to form conductive loops that form one or more inductors, similar to those illustrated in
Referring now to
In an embodiment, an inductor 810 similar to embodiments described above may be integrated into the package substrate 870 or the board 880, or the package substrate 870 and the board 880. Embodiments include any number of inductors 810 formed into the package substrate 870 and the board 880. For example, a plurality of inductors 810 may be integrated into the circuitry of the package substrate 870 or the board 880, or the package substrate 870 and the board 880 for power management, filtering, or any other desired use.
These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
The communication chip 906 enables wireless communications for the transfer of data to and from the computing device 900. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 906 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 900 may include a plurality of communication chips 906. For instance, a first communication chip 906 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 906 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. In some implementations of the invention, the integrated circuit die of the processor may include inductors with fully embedded magnetic cores in accordance with embodiments described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
The communication chip 906 also includes an integrated circuit die packaged within the communication chip 906. In accordance with another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices, such as devices that may include inductors with fully embedded magnetic cores in accordance with embodiments described herein.
The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
Example 1 may include an inductor, comprising: a substrate core; a magnetic core embedded within the substrate core; a first dielectric layer over a first surface of the magnetic core; a second dielectric layer over a second surface of the magnetic core; and a conductive loop around the magnetic core, wherein the magnetic core is separated from the conductive loop by the substrate core, the first dielectric layer, and the second dielectric layer.
Example 2 may include the inductor of Example 1, wherein a plurality of conductive loops are formed around the magnetic core.
Example 3 may include the inductor of Example 1 or Example 2, wherein a plurality of magnetic cores are surrounded by the conductive loop.
Example 4 may include the inductor of Examples 1-3, wherein the conductive loop comprises plated through-hole vias disposed through the substrate core.
Example 5 may include the inductor of Examples 1-4, wherein a first plated through-hole vias is disposed adjacent to a first sidewall of the magnetic core and a second plated through-hole via is disposed adjacent to a second sidewall of the magnetic core.
Example 6 may include the inductor of Examples 1-5, wherein the conductive layers of the first and second through-hole vias are separated from the magnetic core by portions of the substrate core.
Example 7 may include the inductor of Examples 1-6, wherein the conductive loop further comprises a first trace over a first surface of the substrate core and second trace over a second surface of the substrate core.
Example 8 may include the inductor of Examples 1-7, wherein the first trace is separated from the magnetic core by the first dielectric layer and the second trace is separated from the magnetic core by the second dielectric layer.
Example 9 may include the inductor of Examples 1-8, wherein the through-hole vias pass through the first dielectric layer and the second dielectric layer.
Example 10 may include a multi-phase voltage regulator, comprising: a substrate core; a plurality of inductors, wherein the inductors comprise a conductive loop in and around the substrate core, wherein the conductive loops are electrically coupled to a voltage out line; and a magnetic core surrounded by the conductive loops, wherein the magnetic core is separated from surfaces of the conductive loops by the substrate core.
Example 11 may include the multi-phase voltage regulator of Example 10, wherein the magnetic core is separated from the surface of the conductive loops by the substrate core and by a first dielectric layer formed over a first surface of the magnetic core and a second dielectric layer formed over the second surface of the magnetic core.
Example 12 may include the multi-phase voltage regulator of Example 10 or Example 11, wherein the conductive loops surround different magnetic cores.
Example 13 may include the multi-phase voltage regulator of Examples 10-12, wherein conductive loops surround a plurality of magnetic cores.
Example 14 may include the multi-phase voltage regulator of Examples 10-13, wherein a single magnetic core is surrounded by the plurality of conductive loops.
Example 15 may include the multi-phase voltage regulator of Examples 10-14, wherein one or more of the plurality of inductors includes a conductive loop with two or more turns.
Example 16 may include a method for forming an inductor with a fully embedded magnetic core, comprising: forming an opening through a substrate core; filling the opening with a magnetic material to form a magnetic core; disposing a first dielectric layer over a first surface of the magnetic core; disposing a second dielectric layer over a second surface of the magnetic core; and forming through hole vias through the substrate core, wherein surfaces of the magnetic core are separated from the vias by the substrate core.
Example 17 may include the Example of claim 16, further comprising: forming a plurality of openings through the substrate core; and filling the plurality of openings with a magnetic material to form a plurality of magnetic cores.
Example 18 may include the method of Example 16 or Example 17, wherein the magnetic material is a plugging material that is plugged into the opening and cured.
Example 19 may include the method Examples 16-18, wherein the first dielectric layer and the second dielectric layer are laminated over the first and second surfaces of the magnetic core.
Example 20 may include the method of Examples 16-19, wherein the vias are plated through-hole vias.
Example 21 may include the method of Examples 16-20, wherein the vias are lithographically or laser drill defined vias.
Example 22 may include the method of Examples 16-21, wherein the magnetic core is fully embedded by the substrate core, the first dielectric layer, and the second dielectric layer prior to forming the vias.
Example 23 may include an integrated circuit package comprising: an integrated circuit die; a multi-phase voltage regulator electrically coupled to the integrated circuit die, wherein the multi-phase voltage regulator comprises: a substrate core; a plurality of inductors, wherein the inductors comprise a conductive loop in and around the substrate core, wherein the conductive loops are electrically coupled to a voltage out line; and a magnetic core surrounded by the conductive loops, wherein the magnetic core is separated from surfaces of the conductive loops by the substrate core.
Example 24 may include the integrated circuit package of Example 23, further comprising a plurality of magnetic cores within the conductive loops.
Example 25 may include the integrated circuit package of Example 23 or 24, further comprising: a first dielectric layer over a first surface of the magnetic core; and a second dielectric layer over a second surface of the magnetic core.
