Claims
- 1. memory device comprising:a memory array; a controller, coupled to the memory array, including pipeline circuitry for storing a sequence of at least three pending memory operations, wherein the at least three pending memory operations can include any sequence of read and write operations; wherein the pipeline circuitry includes read operation processing circuitry that, when the pipeline circuitry stores a read operation and a write operation having identical addresses, and the read operation is later in the sequence than the write operation, processes the read operation by accessing data stored in the pipeline circuitry for the write operation instead of accessing data in the memory array.
- 2. The memory device of claim 1, wherein the memory device performs write and read operations without an idle cycle between the read operation and the write operation when switching from the read operation to the write operation and when switching from the write operation to the read operation.
- 3. The device of claim 2 wherein the controller comprises:a first address register; a second address register coupled to the first address register; a third address register coupled to the second address register; a memory array; a first data register coupled to the memory array; a second data register coupled to the first data register; a first comparator coupled to the first, second and third address registers; a second comparator coupled to the first, second and third address registers.
- 4. The device of claim 1 wherein the controller has storage circuitry for storing two pending write operations.
- 5. The device of claim 3 wherein the controller further comprises:pipeline circuitry for performing a read operation while storing the two pending write operations; pipeline circuitry for performing a write operation while storing the two pending write operations.
- 6. The device of claim 5 wherein the memory device is an SRAM.
- 7. The device of claim 6, wherein the SRAM performs write and read operations without an idle cycle between the read operation and the write operation when switching from the read operation to the write operation and when switching from the write operation to the read operation.
- 8. The device of claim 7 wherein the controller comprises:a first address register; a second address register coupled to the first address register; a third address register coupled to the second address register; a memory array; a first data register coupled to the memory array; a second data register coupled to the first data register; a first comparator coupled to the first, second and third a memory array; a second comparator coupled to the first, second and third address registers.
- 9. A method of controlling a memory device comprising:storing a sequence of at least three pending memory operations in a pipeline, the sequence of pending memory operations including a read operation and a write operation having identical addresses, wherein the read operation is later in the sequence than the write operation; and processing the read operation by accessing data stored in the pipeline for the write operation instead of accessing data in a memory array.
RELATED APPLICATION
This application is a continuation application of Ser. No. 09/429,849, filed Oct. 28, 1999, which is a divisional of U.S. application Ser. No. 09/253,577, filed Feb. 19, 1999 (now U.S. Pat. No. 6,094,399), which is a continuation of Ser. No. 08/864,456, (now U.S. Pat. No. 5,875,151 filed May 28, 1997, which is a divisional application of Serial No. 08/635,128, filed Apr. 19, 1996 (now U.S. Pat. No. 5,838,831).
US Referenced Citations (36)
Non-Patent Literature Citations (2)
Entry |
Prince, Semiconductor Memories: A Handbook of Design, Manufacture and Application, 2d ed., 1991, pp. 467-472. |
IBM Preliminary, IBM04361RLAB, IBM041811RLAB, 32K X 36 & 64K X 18 SRAM, IBM Corporation (1996), pp. 1-20. |
Continuations (2)
|
Number |
Date |
Country |
Parent |
09/429849 |
Oct 1999 |
US |
Child |
09/625382 |
|
US |
Parent |
08/864456 |
May 1997 |
US |
Child |
09/253577 |
|
US |