Claims
- 1. A fuse trim circuit comprising:
- a first fuse having a first end coupled to a probe voltage node;
- a first logic gate having a first input coupled to a second end of the first fuse;
- a first current source coupled to the second end of the first fuse; and
- a first flip flop having a clock coupled to the probe voltage node, a reset input coupled to a test signal node, and an output coupled to a second input of the first logic gate, wherein the first flip flop is a T-flip flop.
- 2. The circuit of claim 1 wherein the fuse is a polysilicon fuse.
- 3. The circuit of claim 1 wherein the logic gate is an OR gate.
- 4. A fuse trim circuit comprising:
- a first fuse having a first end coupled to a probe voltage node;
- a first logic rate having a first input coupled to a second end of the first fuse;
- a first current source coupled to the second end of the first fuse;
- a first flip flop having a clock coupled to the probe voltage node, a reset input coupled to a test signal node, and an output coupled to a second input of the first logic gate, wherein the first flip flop is a T flip flop;
- a second fuse having a first end coupled to the probe voltage node;
- a second logic gate having a first input coupled to a second end of the second fuse;
- a second current source coupled to the second end of the second fuse; and
- a second flip flop having a clock coupled to the output of the first flip flop, a reset input coupled to the test signal node, and an output coupled to a second input of the second logic gate.
- 5. The circuit of claim 4 wherein the first and second flip flops are T flip flops.
- 6. The circuit of claim 4 wherein the first and second logic gates are OR gates.
- 7. The circuit of claim 4 further comprising:
- a third fuse having a first end coupled to the probe voltage node;
- a third logic gate having a first input coupled to a second end of the third fuse;
- a third current source coupled to the second end of the third fuse; and
- a third flip flop having a clock coupled to the output of the second flip flop, a reset input coupled to the test signal node, and an output coupled to a second input of the third logic gate.
- 8. The circuit of claim 7 further comprising:
- a fourth fuse having a first end coupled to the probe voltage node;
- a fourth logic gate having a first input coupled to a second end of the fourth fuse; and
- a fourth current source coupled to the second end of the fourth fuse; and
- a fourth flip flop having a clock coupled to the output of the third flip flop, a reset input coupled to the test signal node, and an output coupled to a second input of the fourth logic gate.
- 9. The circuit of claim 8 wherein the third and fourth flip flops are T flip flops.
- 10. The circuit of claim 8 wherein the third and fourth logic gates are OR gates.
Parent Case Info
This application claims priority under 35 USC .sctn. 119 (e) (1) of provisional application No. 60/090,748 filed Jun. 26, 1998.
US Referenced Citations (4)