Patent Grant
7988556
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
The illustrative embodiments relate to an electronic game and communications device and, more specifically, to a console configuration for a portable, handheld electronic game with dual screens. Certain of the illustrative embodiments also relate to a portable game machine including two or more display units, on each of which a three-dimensional game image, generated by a three-dimensional image processing unit, is displayed.
Portable, handheld game devices are by now well known in the art. See, for example, U.S. Pat. Nos. 6,716,103; 6,743,104; 6,821,204. Game devices previously have not had, for example, dual screen functionality in combination with touch-sensitive technology.
In an example embodiment, a portable, handheld electronic game device is provided in a unique console configuration, outfitted and arranged for easy access to various functional features and related aspects of the game device.
Generally, the portable game device in the example embodiment is made up of a main body and a cover body that is pivotally attached to the main body for movement between open and closed positions. Twin, backlit, color liquid crystal displays (LCD's) are provided, one on each of the inner surfaces of both the main body and cover body such that, when the cover body is pivoted over the main body to the closed position, the display screens substantially overlie one another and are hidden from view (and thus protected). Each LCD is a three inch screen that can reproduce true 3-D views, and at least one of the screens also employs touch-sensitive technology for enhanced interaction with associated games. To further enhance the interactive experience, a stylus is provided with the game for activating the touch screen, and a blind bore is provided in the main body for storing the stylus when it is not being used.
The main body of the device is also provided with all of the game control buttons. Most of the control buttons are on the inner face of the main body, on either side of the display screen, along with microphone, recharge, and power indicators. The rearward portion of a peripheral edge surrounding the main body also supports an additional pair of buttons for game control. The peripheral edge of the main body also provides access to various other features and functions of the device. For example, a forward portion of the peripheral edge incorporates a volume control slide, a first game card slot as well as headphone/microphone connectors. The rearward portion of the peripheral edge is provided with, in addition to the control buttons, an external extension connector for connecting an AC adaptor that can be used to either recharge the internal battery or to operate the game device using household power; a wrist strap attachment mechanism; the stylus port; and a second game slot. This second game card slot may, for example, accommodate game cards from other game systems such as other game systems manufactured by the assignee of this application.
In addition to the LCD on the inner face of the cover body, the latter is also provided with a pair of stereo speakers, one on either side of the display screen.
In accordance with a feature of an example embodiment, the portable game machine includes hardware/software capable of simultaneously displaying different three-dimensional images on two display units by using a single three-dimensional image processing unit without causing flicker on the display screens.
Also, another feature of an example embodiment is to make it possible for a portable game machine to include two display units, at least one two-dimensional image processing unit, and a single three-dimensional image processing unit, wherein a game image generated by the two-dimensional image processing unit is displayed on one of the display units and a game image generated by the three-dimensional image processing unit is displayed on the other display unit, and to simultaneously display different three-dimensional game images on the two display units without adding another three-dimensional image processing unit or substantially changing the configuration of the portable game machine.
Example handheld portable game devices and emulators of these handheld portable game devices will now be described in detail in connection with the drawings identified below.
a)-26(f) show example registers of the example portable game system;
a) and 27(b) show an example of a touch panel display structure usable for the example portable game system;
a)-32(c) show example alternative compatible implementations; and
a) and 33(b) show example graphics display modes.
Referring to
A first display screen 32 is recessed within the upper face 26 of the main body 12 with dimensions of approximately 2 inches in length and 1⅞ inches in width, yielding a diagonal screen dimension of 3 inches. The screen in the example embodiment is a backlit (e.g., 40 candelas), color liquid crystal display (LCD) with a display resolution of 256×192 dots (aspect ratio 4:3). This screen is touch sensitive and may be activated by a stylus, described further herein. A power button 34 is located in the upper left corner of face 26 and is used to turn the game console on and off. A cross-shaped directional control button 36 is located adjacent and below the power button 34, and is used for game play control.
More specifically, display screen 32 includes a resistive-membrane touch panel that allows coordinates to be obtained in dot units. The touch panel can be operated with a finger or a stylus. The touch panel input data includes x-coordinate (e.g., 8 bits); y-coordinate (e.g., 8 bits); touch determination flag (e.g., 1 bit); and data validity flag (e.g., 2 bits). In the example portable game system, the touch panel must be pressed down with a force that exceeds a specified value, e.g., 80 g, for the location to be detected. The details of the input data for the touch panel are shown below:
a) and 27(b) show an example touch panel structure which includes an upper film 902, a lower film 904, transparent conducting membranes 906, 908 and dot spacers 910. As shown in
In the example portable game system, the touch panel structure extends over all or substantially all of the display screen. It is of course possible, if desired, to provide the touch input only over a portion of the display screen.
In the upper right corner of the main body 12, there are side-by-side “start” and “select” buttons 38, 40, respectively, with X/Y/A/B buttons 42 located adjacent and below the “start” and “select” buttons. Buttons 38, 40 and 42 are also used for game play control. A microphone 44 (which may, for example, be an omni-directional condenser microphone) is located below the left edge of screen 32 for use with specially designed games or other applications (e.g., voice chat) having a microphone feature. A battery recharge indicator LED 46 and a power indicator LED 48 are also located on the upper face 26, adjacent the lower edge thereof, below the right edge of screen 32.
With reference now especially to
As best seen in
The stylus 71 is a plastic pencil-shaped device with a rounded tip 73 and is used to activate the touch screen 32.
A pair of left, right control buttons (or shoulder buttons) 72, 74 are located on the peripheral edge 30, at the corners where the upper portion 60 of the peripheral edge 30 meets the side portions 76, 78 of the peripheral edge. The location of these buttons and the location of previously described buttons 34, 36 and 42 facilitate manipulation game control by the user's thumbs and index fingers when the game is held with two hands in a natural and intuitive manner.
The lower (or outer) face 28 of the main body is provided with a battery cover 80 (
The cover body 14 also has an upper (or inner) face 82 (
As already noted, the game card slot 58 is sized and adapted to receive a conventional game card designed for the by now well known Nintendo Gameboy Advance System®. Accordingly, the game card per se for slot 58 does not form any part of this invention and need not be described further.
The new game or memory card 100 designed especially for use with this game device is shown in
The game or memory card 100 is preferably of molded plastic construction and has substantially planar upper and lower surfaces 102, 104, respectively, a forward edge 106, rearward edge 108 and side edges 110, 112. The forward end of the upper surface 102 is formed with a rectangular recess 114 in which a plurality of terminal strips 116 are located, extending from a rear wall 118 of the recess to the forward edge 106 of the card. The rearward wall 115 of the recess is substantially perpendicular to the upper and lower surfaces 102, 104 but, as a practical matter, is sloped by no more than about 3 degrees simply to facilitate removal of the card from the mold during manufacture of the card. The terminal strips 116 are parallel to each other and are separated by raised ribs 120 that also extend from the rear wall 118 to the forward edge 106. The free ends 122 of the ribs 120 are chamfered as best seen in
An enlarged radius 124 is formed at forward corner 126 where the side edge 110 meets forward edge 106. A first notch 128 is formed in corner 126, defined by a vertical notch side wall 130, a vertical notch back wall 132 and a flat notch bottom wall 134. The latter is parallel to the upper and lower card surfaces 102, 104, while notch side wall 130 is parallel to side edges 110, 112, and notch back wall is perpendicular to the notch side wall 130 and parallel to the card forward edge 106. The depth of the notch is about half the approximate ⅛ inch thickness of the card, and the length of the notch is about ¼ inch, which in turn, is about half the length of the recess 114. Rearwardly of the notch 128, along the card side edge 110, there is formed a second notch 136 that opens to the side of the card, defined by parallel side walls 140, 142 and a back wall 144. Side walls 140, 142 are parallel to forward and rearward card edges 106, 108 while back wall 144 is parallel to card side edges 110, 112. An angled surface 145 connects back wall 144 to the edge 110. Here again, the depth of the notch is about half the thickness of the card, and the length of the notch is about ⅛ inch.
Notches 128 and 136 cooperate with components of a “push-push” mechanism inside the game slot 64 to provide controlled, spring-loaded movement of the game card during insertion and ejection.
The opposite forward corner 146 of the card where side edge 112 meets forward edge 106 is defined by a smaller radius than radius 124. Note that the forward surfaces 148, 150 of the card on either side of the recess 114 are also chamfered to substantially the same degree as the chamfer on ribs 120.
Side edge 112 is stepped along its entire length in the upper plane of the card only, as defined by horizontal shoulder 152 that is parallel to upper and lower surfaces 102, 104 and a recessed edge portion shoulder 154 that is parallel to the side edges 110, 112. This shoulder insures correct orientation of the card when inserted into a game system slot.
The rearward edge 108 of the card is substantially uniform in profile from side edge 110 to side edge 112, with both rearward corners 156, 158 rounded by a radii similar to the radius at corner 146.
The dimensions of the card are matched to the game system entry slot, and in the exemplary embodiment, the card 100 is substantially square, with a length dimension (front-to-back) of 1⅜″, and a width dimension (side-to-side) of 1¼″.
When inserted into the game system entry slot, card 100 is electrically connected via the terminal strips 116 to the processing circuitry of the example portable game system. In this way, the processing circuitry can access the electrical components on the card. For example, if the card includes a memory, the processing circuitry can read data from and/or write data to the memory on the card. The electrical components on the card are of course not limited a memory.
More specifically, when card 100 is inserted into the game system entry slot of the example portable game system, the terminal strips 116 electrically contact or mate with corresponding electrical contacts within example portable game system. This action electrically connects the electrical components to the electronics within the example portable game system. The electrical components of card 100 may include a ROM that stores instructions and other information pertaining to a particular video game. The ROM for one card 100 may, for example, contain instructions and other information for an adventure game while the ROM of another card 100 may contain instructions and other information for a car race game, an educational game, etc. To play a game, a user of the example portable game system need only connect an appropriate card 100 into slot 58—thereby connecting the card's ROM (and any other circuitry it may contain) to the example portable game system. This enables the electronics of the example portable game system to access information contained within the ROM, which information controls the game system to play the appropriate video game by displaying images and reproducing sound as specified under control of the ROM game program information.
Furthermore, the CPU 223 is electrically connected to the external memory I/F 226, in which the cartridge 217 is inserted. The cartridge 217 is a storage medium for storing the game program and, specifically, includes a program ROM 217a for storing the game program and a backup RAM 217b for rewritably storing backup data. The game program stored in the program ROM 217a of the cartridge 217 is loaded to the work RAM 224 and is then executed by the CPU 223. In the present embodiment, an exemplary case is described in which the game program is supplied from an external storage medium to the portable game machine 200. However, the game program may be stored in a non-volatile memory incorporated in advance in the portable game machine 200, or may be supplied to the portable game machine 200 via a wired or wireless communication circuit.
The three-dimensional image processing unit 231 is connected to the 3D line buffer 232. The 3D line buffer 232 is a buffer memory for temporarily retaining image data for one scanning line of the first LCD 211 (or the second LCD 212). The image data generated by the three-dimensional image processing unit 231 is stored in this 3D line buffer 232 sequentially by one line.
The 3D line buffer 232 is connected to a capture circuit 233 and an LCD selector (SEL LCD) 235. The capture circuit 233 sequentially reads image data for one line stored in the 3D line buffer 232 and then sequentially stores the read image data in the VRAM 221, which will be described further below, thereby capturing the game image generated by the three-dimensional image processing unit 231.
The capture circuit 233 is connected to a VRAM selector (SEL VRAM) 234. The VRAM 221 is provided with two VRAMs, that is, a first VRAM 221a and a second VRAM 221b. Instead of these two first and second VRAMs 221a and 221b, a single VRAM may be used with its two different storage areas being used as the first VRAM 221a and the second VRAM 221b. The VRAM selector 234 switches an output destination of the capture circuit 233 between the first VRAM 221a and the second VRAM 221b.
The first VRAM 221a and the second VRAM 221b are connected to a VRAM selector (SEL VRAM) 236. The VRAM selector 236 switches a source of data to the two-dimensional image processing unit 237 between the first VRAM 21a and the second VRAM 221b.
The two-dimensional image processing unit 237 is connected to a 2D line buffer 238. As with the 3D line buffer 232, the 2D line buffer 238 is a buffer memory for temporarily retaining image data for one scanning line of the second LCD 212. The image data generated by the two-dimensional image processing unit 237 is stored in this 2D line buffer 238 sequentially by one line.
The 2D line buffer 238 is connected to an LCD selector 235. The LCD selector 235 switches an output destination of the 3D line buffer 232 between the first LCD 211 and the second LCD 212, and an output destination of the 2D line buffer 238 between the first LCD 211 and the second LCD 212. In the present embodiment, the LCD selector 235 performs control such that, when the output of the 3D line buffer 232 is supplied to the first LCD 11, the output of the 2D line buffer 38 is supplied to the second LCD 212, and when the output of the 3D line buffer 232 is supplied to the second LCD 212, the output of the 2D line buffer 238 is supplied to the first LCD 211.
The portable game machine 200 has the above-described structure. Generally, the game image generated by the three-dimensional image processing unit 231 is supplied via the 3D line buffer 232 and the LCD selector 235 to the first LCD 211, while the game image generated by the two-dimensional image processing unit 237 is supplied via the 2D line buffer 238 and the LCD selector 235 to the second LCD 212. As a result, the three-dimensional game image generated by the three-dimensional image processing unit 231 is displayed on the first display screen 211a, while the two-dimensional game image generated by the two-dimensional image processing unit 237 is displayed on the second display screen 212a. However, the present embodiment has a feature in which the above-structured portable game machine 200 is used to display different three-dimensional game images on two display screens, that is, the first display screen 211a and the second display screen 212a. Hereinafter, the operation of the portable game machine 200 according to the present embodiment is described.
The portable game machine 200 alternately performs operations with periods of one frame. Hereinafter, the operation of the portable game machine 200 is described as being divided into a process in an odd-numbered frame and a process in an even-numbered frame. Note that the “odd-numbered frame” and the “even-numbered frame” are merely so called for convenience. In other words, if one frame is assumed to be an odd-numbered frame, frames before and after that frames are even-numbered frames. Conversely, if one frame is assumed to be an even-numbered frame, frames before and after that frames are odd-numbered frames.
In the present embodiment, the three-dimensional image processing unit 231 generates a game image representing a state in a virtual three-dimensional game space captured by virtual cameras different for odd-numbered and even-numbered frames.
Examples of the game screen displayed on the first display screen 211a and the second display screen 212a based on the above-described operation of the portable game machine 200 are illustrated in
As such, in the present embodiment, a real-time image and a captured image are alternately displayed on the first display screen 11a and the second display screen 212a. Then, on the first display screen 211a, a game image representing the state of the virtual three-dimensional game space captured by the first virtual camera is displayed, while on the second display screen 212a, a game image representing the state of the virtual three-dimensional game space captured by the second virtual camera is displayed. Note that, as evident from
With reference to
In
The CPU 223 then determines whether the current frame is an odd-numbered frame (S14).
When the current frame is an odd-numbered frame, the CPU 223 allocates the first LCD 211 as the output destination of the 3D line buffer 232 and the second LCD 212 as the output destination of the 2D line buffer 238 (S15). Furthermore, the CPU 223 allocates the first VRAM 221a as the output destination of the capture circuit 233 (S16), and the second VRAM 221b to the two-dimensional image processing unit 237 (S17). Thereafter, an odd-numbered frame rendering/displaying process (S18) is performed, and then the procedure goes to step S23. Details of the odd-numbered frame rendering/displaying process are described further below.
On the other hand, when the current frame is an even-numbered frame, the CPU 223 allocates the second LCD 212 as the output destination of the 3D line buffer 232 and the first LCD 211 as the output destination of the 2D line buffer 238 (S19). Furthermore, the CPU 223 allocates the second VRAM 221b as the output destination of the capture circuit (S20) and the first VRAM 221a to the two-dimensional image processing unit 237 (S21). Thereafter, an even-numbered frame rendering/displaying process (S22) is performed, and then the procedure goes to step S23. Details of the even-numbered frame rendering/displaying process are described further below.
In step S23, the CPU 223 determines whether the game is over. If the game continues, the procedure returns to step S12. If the game is over, the procedure ends.
Next, the details of the odd-numbered frame rendering/displaying process are described with reference to
First, the geometry engine of the three-dimensional image processing unit 231 converts vertex coordinates (in the world coordinate system) of each polygon in the virtual three-dimensional game space to the two-dimensional projection coordinate system (S32). When conversion of the vertex coordinates of each polygon is completed, an instruction for starting a display process is issued from the GPU 222 to the rendering engine of the three-dimensional image processing unit 231 and the 2D rendering engine of the two-dimensional image processing unit (S33). Upon reception of this instruction, the rendering engine of the three-dimensional image processing unit 231 and the 2D rendering engine of the two-dimensional processing unit concurrently perform their respective processes.
Upon reception of the display process starting instruction, the rendering engine of the three-dimensional image processing unit 231 generates image data for the first one line through a rendering process based on the results of conversions of the vertex coordinates of each polygon, and then stores the generated image data in the 3D line buffer 232 (S34). Then, the image data for one line stored in this 3D line buffer 232 is supplied to the first LCD 211, and is then displayed on the first display screen 211a (S35). Also, the image data for one line stored in the 3D line buffer 232 is stored in a predetermined area of the first VRAM 221a by the capture circuit 233 (S36). Then, after waiting for an H blank timing (horizontal blanking period) in order to establish horizontal synchronization (S37), the rendering engine performs a process similar to the above for the next line. That is, the rendering engine of the three-dimensional image processing unit 231 generates image data for the next one line, and then stores the generated image data in the 3D line buffer 232 (S34). Thereafter, until all lines have been completely processed (that is, until the entire screen has been completely processed), processes of steps S34 through S37 are repeated.
Upon reception of the display process starting instruction, the 2D rendering engine of the two-dimensional image processing unit 237 reads image data for the first one line of the game image stored in the second VRAM 221b, and then stores the read image data in the 2D line buffer 238 (S39). Then, the image data for one line stored in this 2D line buffer 238 is supplied to the second LCD 212, and is then displayed on the second display screen 212a (S40). Then, after waiting for an H blank timing (horizontal blanking period) in order to establish horizontal synchronization (S41), the 2D rendering engine performs a process similar to the above. That is, the 2D rendering engine of the two-dimensional image processing unit 237 reads image data for the next one line from the second VRAM 221b, and then stores the read image data in the 2D line buffer 238 (S39). Thereafter, until all lines have been completely processed (that is, until the entire screen has been completely processed), processes of steps S39 through S41 are repeated.
When all lines have been completely processed by the rendering engine of the three-dimensional image processing unit 231 and the 2D rendering engine of the two-dimensional image processing unit 237, the odd-numbered frame rendering/displaying process ends.
Next, the details of the even-numbered frame rendering/displaying process are described with reference to
First, the geometry engine of the three-dimensional image processing unit 231 converts vertex coordinates (in the world coordinate system) of each polygon in the virtual three-dimensional game space to the camera coordinate system (S51). Furthermore, the geometry engine of the three-dimensional image processing unit 231 converts these vertex coordinates (in the camera coordinate system) to the two-dimensional projection coordinate system (S52). When conversion of the vertex coordinates of each polygon is completed, an instruction for starting a display process is issued from the GPU 222 to the rendering engine of the three-dimensional image processing unit 231 and the 2D rendering engine of the two-dimensional image processing unit (S53). Upon reception of this instruction, the rendering engine of the three-dimensional image processing unit 231 and the 2D rendering engine of the two-dimensional processing unit concurrently perform their respective processes.
Upon reception of the display process starting instruction, the rendering engine of the three-dimensional image processing unit 231 generates image data for the first one line through a rendering process based on the results of conversions of the vertex coordinates of each polygon, and then stores the generated image data in the 3D line buffer 232 (S54). Then, the image data for one line stored in this 3D line buffer 232 is supplied to the second LCD 212, and is then displayed on the second display screen 212a (S55). Also, the image data for one line stored in the 3D line buffer 232 is stored in a predetermined area of the second VRAM 221b by the capture circuit 233 (S56). Then, after waiting for an H blank timing (horizontal blanking period) in order to establish horizontal synchronization (S57), the rendering engine performs a process similar to the above for the next line. That is, the rendering engine of the three-dimensional image processing unit 231 generates image data for the next one line, and then stores the generated image data in the 3D line buffer 232 (S54). Thereafter, until all lines have been completely processed (that is, until the entire screen has been completely processed), processes of steps S54 through S7 are repeated.
Upon reception of the display process starting instruction, the 2D rendering engine of the two-dimensional image processing unit 237 reads image data for the first one line of the game image stored in the first VRAM 221a, and then stores the read image data in the 2D line buffer 238 (S59). Then, the image data for one line stored in this 2D line buffer 238 is supplied to the first LCD 211, and is then displayed on the first display screen 211a (S60). Then, after waiting for an H blank timing (horizontal blanking period) in order to establish horizontal synchronization (S61), the 2D rendering engine performs a process similar to the above. That is, the 2D rendering engine of the two-dimensional image processing unit 237 reads image data for the next one line from the first VRAM 221a, and then stores the read image data in the 2D line buffer 238 (S59). Thereafter, until all lines have been completely processed (that is, until the entire screen has been completely processed), processes of steps S59 through S61 are repeated.
When all lines have been completely processed by the rendering engine of the three-dimensional image processing unit 231 and the 2D rendering engine of the two-dimensional image processing unit 237, the even-numbered frame rendering/displaying process ends.
As described above, according to the portable game machine 200 of the present embodiment, by using the single three-dimensional image processing unit 231, different three-dimensional game images can be simultaneously displayed on the first LCD 211 and the second LCD 212 without flicker on the display screens.
As described above, when generating a normal two-dimensional game image, the two-dimensional image processing unit 237 disposes a two-dimensional image representing a character on the virtual screen called a “sprite” and a two-dimensional image representing a background on the virtual screen called a “screen”, and then synthesizes these virtual screens to generate a game image to be eventually displayed. There might be the case where a plurality of “screens” are present.
The capture circuit 233 stores the game image captured in each odd-numbered frame in the sprite area 221c of the VRAM 221 and the game image captured in each even-numbered frame in the screen area 221d of the VRAM 221. When generating a normal two-dimensional game image, the two-dimensional image processing unit 237 generates a two-dimensional game image formed by synthesizing the “sprite” and the “screen” and then outputs the generated image to the 2D line buffer 238. In the exemplary modification, however, in each odd-numbered frame, the two-dimensional image processing unit 237 generates a game image formed of only the “screen”, and then outputs the generated game image via the 2D line buffer 238 to the second LCD 212. In each even-numbered frame, the two-dimensional image processing unit 237 generates a game image formed of only the “sprite”, and then outputs the generated game image via the 2D line buffer 238 to the first LCD 211. As a result, game images similar to those shown in
As such, selecting a desired virtual screen from a plurality of virtual screens for display is a function originally provided to the two-dimensional image processing unit 237. Therefore, no special function has to be added to the two-dimensional image processing unit. Also, an additional storage area for temporarily storing the game image captured by the capture circuit 233 is not required, thereby suppressing cost required for the portable game machine 200.
The following devices connect to the ARM7 sub-processor: the wireless communications circuit, a portion of the digital keys, the sound, touch screen, microphone, real time clock (RTC) and built-in flash memory. These devices may be accessed using an Application Program Interface (API) regardless of what state the ARM7 sub-processor is in. An API is a group of functions that increase efficiency when developing applications and is used in low-level system calls and to control hardware. When an AGB Game Pak is connected to the portable game machine, the sub-processor starts up at 16.777 MHz. In this “AGB Game Pak” mode, the LCD1 screen, the 2D graphics engine, the LCD controller and a part of the VRAM are usable, but the ARMS and ARMS-related peripheral circuitry, the 3D graphics engine and the serial bus are not usable. Because the serial bus becomes unusable, the wireless communication circuitry, the touch screen, the RTC, the microphone and the built-in flash memory connected to that bus are also unusable. In addition, the X and Y buttons become unusable.
An example geometry engine has the following features:
An example rendering engine has the following features:
The example portable game machine includes various memories. System ROM for the ARM9 core is 8 KB (2K×32 bit) and system ROM for the ARM7 core is 16 KB (4K×32 bit). Internal work RAM shared by the ARM9 and the ARM7 is 32 KB (8K×32 bit) and ARM7 dedicated work RAM is 64 KB (16K×32 bit). Work RAM does not have a fixed us and so it can be assigned for each application in the ways that make the most efficient use of memory resources. This ability is called WRAM bank control.
There is a total of 656 KB of VRAM A to VRAM I (128 KB+128 KB+128 KB+128 KB+64 KB+16 KB+16 KB+32 KB+16 KB). VRAM A to I does not have a fixed use, so it can be assigned for each application in the ways that make the most efficient use of memory resources. This ability is called VRAM bank control. For example, VRAM A to D can be used as memory for holding bitmap data during VRAM display mode and it can also be set as memory for writing bitmap data during captures.
The main memory is 4 MB and is connected to the processor as an independent chip. Because the game card bus is not mapped to the processor address space, application and data must be executed after loading them into main memory.
The on-board wireless communication circuit is capable of using the 2.4 GHz bandwidth. The following modes are available:
With reference to
Regions of the LCD screen where no OBJ and BG are displayed are filled with a single color. This region is called the Backdrop and be visualized as a single-color surface that is always displayed furthest in the back, as depicted in
The example portable game system allocates RAM specifically for BG and OBJ palettes (palette RAM). Data stored in palette RAM are called standard palettes. Extended palettes allowing use of 256 colors×16 palettes may also be used. Standard palette RAM is allocated separately for OBJ and for BG in both 2D graphics engine A and 2D graphics engine B. Color 0 in each palette is the transparent color. The Backdrop screen use the color set at the beginning of the BG palette (color 0 of palette 0). Because standard palette RAM resides inside the 2D graphics engines, the 2D graphics engine must be enabled before data can be written to its RAM.
The example portable game system may include window features that can restrict the regions where BGs and OBJs are displayed, as well as the region in which color special effects are applied. In one illustrative implementation, the system may be provided with three kinds of windows: Window 0, Window 1, and the OBJ Window as shown in
OBJ and BG can use special effects such as alpha-blending and fade-in/fade-out effects. These effects can be limited to a region by using windows, as noted above. For alpha-blending, computations are conducted are conducted and a 16-level translucency process is performed on two selected screens. This process is not performed on transparent portions (transparent pixels). Fade-in/Fade-out computations are conducted and a 16-level process of changing the brightness is performed on the selected screen. This process is not performed on transparent portions (transparent pixels).
BGs and OBJs have display priorities associated therewith. Four levels of display priority can be set for BGs using, for example, a BG control register. When BGs have the same priority, the one with the lower BG number has higher priority. The Backdrop screen always has the lowest priority.
Four levels of display priority can be set for OBJs using, for example, OBJ attribute data. When OBJs have the same priority, the one with the lower OBJ number has higher priority.
If an OBJ and a BG have the same priority, the OBJ has higher priority than the BG.
With reference to
For games that utilize only one LCD, the non-used LCD may be disabled.
Thus, on the Display Output A side, there are modes that display the bitmap data in the VRAM and main memory in addition to the mode that displays the images generated by the graphics circuit:
On the Display Output B side, the only mode selection is graphics display ON or OFF.
The portable game machine includes various registers used in the implementation of the above-described functionalities, as well as other functionalities. These registers are in the address space of the CPU core which, for example, be an ARMS core.
A first such register DISPSTAT (Display Status) is shown in
Another register POWCNT (Power Control) is shown in
Another register DISPCNT (Display Control for 2D Graphics Engine A) is shown in
More specifically, O [d31] is an OBJ Extended Palette flag:
BG [d30] is a BG Extended Palette flag which is valid for BG screens that can be displayed with 256 colors×16 palettes:
More specifically, OBJ and each BG screen can be allocated 256 colors×16 palettes (8 KB) of VRAM by setting the Extended Palette flag in the DISPCNT register and a RAM Bank Control register. When allocated, palette slots are not mapped to the CPU bus. To rewrite the palette data, the palette slot must be allocated to the LCD controller.
BG Screen Base Offset [d29-27] offset (in 64-KB units) the base address of the screen data set with a BG control register. For character BG, the BG screen composition elements are treated as characters of 8×8 dots. Consequently, character data is required to display the BG. In addition character index data for each 8×8-dot unit is required; this character index data is called screen data. The base address of the BG screen data is calculated as follows:
The value set in the BG control register+(BG screen base offset×0x100000)
An arbitrary base address can be specified from a maximum 512 KB of BG-VRAM space.
BG Character Base Offset [d26-d24] offset (in 64-KB units) the base address of the screen data set with the BG control register. Consequently, the base address of the BG character data is calculated as follows:
The value set in the BG control register+(BG character base offset×0x100000)
An arbitrary base address can be specified from a maximum 512 KB of BG-VRAM space.
OH [d23] is an OBJ processing during H-Blank period flag. When set to 0, the OBJ render process is performed during the entire H-Line period (including the H-Blank period). When set to 1, the OBJ render process is performed only during the display period, but not during the H-Blank period. In this case, the maximum number of OBJ cannot be displayed.
BM [d22] is a VRAM Extended flag for Bitmap OBJ that specifies OBJ-VRAM capacity when 1D mapping is selected for OBJ bitmap data. “0” specifies 128 KB (starting character name boundary of 128 bytes) and “1” specifies 256 KB (starting character name boundary of 256 bytes).
CH [d21-d20] is a VRAM Region Extended Flag for Character OBJ which specifies OBJ-VRAM capacity when OBJ character data uses 1D mapping:
For OBJ character data, 8×8 dot sections are treated as basic characters and are assigned a Character Number. The OBJ size can be from 8×8 dots to 64×64 dots (12 different sizes). The OBJ character data are defined as having either 16 colors or 256 colors, so the definition of a single basic character requires either 32 bytes or 64 bytes (both have the same format as BG character data).
Display VRAM [d19-d18] selects the VRAM block to display when in a VRAM display mode:
Display mode [d17-d16] selects the display mode:
When the display mode is OFF, the 2D/3D graphics, VRAM display and main memory display are not selected and appear white. Graphics display mode displays both 2D and 3D graphics. VRAM display mode displays the bitmap stored in VRAM. Main memory display mode displays the bitmap data stored in main memory.
As noted above, graphics display mode displays images generated with 2D and 3D graphics features.
OW [d15] is an OBJ Window Display Enable flag that is set to “0” to disable display of the OBJ window and to “1” to enable display of the OBJ window. To display the OBJ window requires enabling both the OBJ Window Display Enable Flag and the OBJ Display Enable Flag (described below).
W1 [d14] is a Window 1 Display Enable flag that is set to “0” to disable display of Window 1 and is set to “1” to enable display of Window 1.
W0 [d13] is a Window 0 Display Enable flag which is set to “0” to enable display of Window 0 and is set to “1” to enable display of Window 0.
O [d12] is an OBJ Display Enable flag which is disables OBJ display when set to “0” and enables OBJ display when set to “1”.
B3 [d11] is a BG3 Display Enable flag for disabling (“0”) and enabling (“1”) display of BG3.
B2 [d10] is a BG2 Display Enable flag for disabling (“0”) and enabling (“1”) display of BG2.
B1 [d09] is a BG1 Display Enable flag for disabling (“0”) and enabling (“1”) display of BG1.
B0 [d08] is a BG0 Display Enable flag for disabling (“0”) and enabling (“1”) display of BG0.
2D Display Forced Blank [d07] is forcedly halted by the CPU. Because 2D display is halted, 3D graphics using BG0 are not displayed either. During a forced blank, the 2D graphics circuitry does not access VRAM and the LCD screen is white. However, even during a forced blank, an internal HV synchronization counter continues to run. If the forced blank setting is changed from ON to OFF during a display period of the internal HV synchronization counter, the effect takes placed immediately; if it is changed from OFF to ON, the switch takes place at the start after 3 lines.
BM [d06-d05] specifies the Bitmap OBJ Data Mapping Mode:
CH [d04] indicates the Character OBJ Data Mapping Mode. “0” indicates 2D mapping and “1” indicates 1D mapping. In 2D mapping mode, only up to 32 KB of OBJ-VRAM can be referenced. In 1D mapping mode, a capacity of 32 to 256 KB can be set with the OBJ-VRAM Region Extended flag. Accordingly, more OBJ characters can be defined in OBJ-VRAM using 1D mapping mode.
2D/3D Display Selection for BG0 [d03] determines whether to use one of the BG screens (BG0) for 2D graphics or for 3D graphics. In an example implementation, setting [d03] to “0” displays 2D graphics and setting [d03] to “1” displays 3D graphics.
BG Mode [d02-d00] set the background mode number for graphics engine A. The background mode selects the BG types that can be used:
A similar display control register (not shown) may be provided for Graphics Engine B. Using this register, a background mode number may be set for graphics engine B. The background mode selects the BG types that can be used:
The 3D BG can display images generated by the 3D graphics engine. It can be displayed with other BG screens according to alpha-blending and priority settings. The 2D graphics engine B cannot use this background type.
The text BG is a character format BG. Text BG is the only BG type that can handle characters defined in 16 colors and control VRAM consumption, but it cannot accommodate affine transformations.
The affine BG is a character format BG that can accommodate affine transformations. It cannot perform character-unit processes such as HV flips.
Affine extended BG are of three types: Character BG that can use 256 colors×16 palettes; 256-Color Bitmap BG; and Direct Color Bitmap BG that can specify color directly.
Large-Screen 256-Color Bitmap BG makes full use of the maximum capacity of BG-VRAM (512 KB). As such, it cannot be used other BG's. However, it can be used together with a 3D screen. 2D graphics engine B cannot use this BG type.
The illustrative portable game system can handle two types of OBJ: Character OBJ and Bitmap OBJ.
Another register MASTER BRIGHT is shown in
E_MOD [d15-d14] sets the mode for processing brightness up/down:
E_VALUE [d04-d00] sets the factors as calculated below:
1. Brightness Up Computation
Rout=Rin+(63−Rin)×(E_VALUE/16)
Gout=Gin+(63−Gin)×(E_VALUE/16)
Bout=Bin+(63−Bin)×(E_VALUE/16)
2. Brightness Down Computation
Rout=Rin−(63−Rin)×(E_VALUE/16)
Gout=Gin−(63−Gin)×(E_VALUE/16)
Bout=Bin−(63−Bin)×(E_VALUE/16)
The result of the Brightness Up and Down computation (Rout, Gout and Bout) is rounded to the nearest integer.
Another register VCOUNT is shown in
Written values to the VCOUNT register are reflected when the hardware's V-Counter is updated. By using this register, cycles of all portable game devices can be synchronized by adjusting the V-count value when communicating among multiple portable game devices. When writing, it is preferable to confirm that the current value of the V-Counter is between 202 and 212, and only values in this range should be written to the register.
Another register DISPCAPCNT (Display Capture Control Register) is shown in
E[d31] is a Display Capture Enable flag. When the flag is set to “1”, one screen's worth of data is captured from the next 0 line, and then the flag is set to “0”.
MOD[d30-d29] specifies the capture mode:
COFS[d27-d26] specify the Read Address Offset for Capture Data Source VRAM. This register is invalid in VRAM display mode. If the offset exceeds 0x20000 during reading, the reading continues after wrapping to address 0x00000.
SRC[d25-d24] specify the Capture Data Source Selection. B[d25] is “0” for VRAM and “1” for Main Memory. A[d24] is “0” for graphics display screen (after 3D/2D blending) and “1” for the 3D screen.
WSIZE[d21-d20] specifies the size when writing the capture data. With RAM captures, one line is always read as a 256-dot image, so no blending and then capturing can occur when the setting is 128×128 dots.
WOFS[d19-d18] specify the Address Offset for Capture Data Write. This can specify the offset value for the address where data is written in the specified VRAM. If the offset exceeds 0x20000 during writing, the writing continues after wrapping to address 0x00000.
DEST[d17-d16] specifies the Capture Data Write Destination VRAM selection. The write destination VRAM must be allocated to the LCD controller.
EVB[d12-d08] and EVA[d04-d00] are blending factors for capture sources A and B. The calculation method is described below.
In VRAM display mode, the VRAM block for display VRAM and for writing the captured image data can be the same.
The capture data format is shown in
The calculation of the data to write is as follows.
1. For data captured from source A:
CAP=Ca
Capture source A's alpha value is used for the alpha value.
2. For data captured from source B:
CAP=Cb
Capture source B's alpha value is used for the alpha value.
3. For capturing data blended from sources A and B:
CAP=[(Ca×Aa×EVA)+(Cb×Ab×EVB)]/16
The alpha value is one when EVA is non-zero and capture source A's alpha value is one, or when EVB is non-zero and capture source B's alpha value is one. In all other circumstances, the alpha value is zero.
When a conflict occurs between access to the display circuit VRAM and access to VRAM from the CPU, the display circuit VRAM access takes precedence. Because the dot clock of the LCD controller is ⅙ of a cycle of the image processing clock and the system clock, the timing of the LCD controller to access the VRAM is once every six cycles. If the VRAM of the capture is being displayed while display capturing, the frequency at which the display circuit accesses the VRAM is doubled, and the VRAM is accessed with a timing of once every three cycles. With this timing, when simultaneously accessing from the CPU, the CPU access must wait one cycle.
Some or all of the above-described system components could be implemented as other than the hand-held system configurations described above.
An emulator system, for example, might include software and/or hardware components that emulate or simulate some or all of hardware and/or software components of the system for which the application software was written. For example, the emulator system could comprise a general-purpose digital computer such as a personal computer, which executes a software emulator program that simulates the hardware and/or firmware of the system. The emulator could also comprise a personal digital assistant (PDA) that simulates the hardware and/or firmware of the system. An emulator may execute the game software so that a particular game functions and/or appears somewhat differently from how it functions and/or appears on its intended platform. Thus, the emulator may show a color game in monochrome or a play a game without its accompanying sound. Emulation as used herein is intended to include emulation that results in these and other such differences in function and appearance.
Some general purpose digital computers (e.g., IBM or MacIntosh personal computers and compatibles) are equipped with 3D graphics cards that provide 3D graphics pipelines compliant with DirectX or other standard 3D graphics command APIs. They may also be equipped with stereophonic sound cards that provide high quality stereophonic sound based on a standard set of sound commands. Such multimedia-hardware-equipped personal computers running emulator software may have sufficient performance to approximate the graphics and sound performance of the system. Emulator software controls the hardware resources on the personal computer platform to simulate the processing, graphics, sound, peripheral and other capabilities of the portable game system platform for which the game programmer wrote the game software. Similarly, PDAs and other hand-held communication devices such as mobile telephones running emulator software may have sufficient performance to approximate the graphics and sound performance of the system.
U.S. Pat. No. 6,672,963 (the contents of which are incorporated herein in their entirety) discloses a software emulator that maintains high-quality graphics and sound in real time across a wide variety of video games and other applications. The emulator disclosed in the '963 patent achieves this through a unique combination of features and optimizations including, for example:
It will be recognized that some or all of the various features and optimizations described in the '963 patent are applicable to emulate the example portable game systems described herein.
As described below, an emulator for the example portable game system described above may run on a hand-held computing system such as a PDA or a hand-held communication device such as a mobile telephone. Such devices typically have a single display screen and thus the emulator will need to determine how to present Display Output A and Display Output B (see, e.g.,
For example, the emulator could effectively divide the single display screen into two display areas and respectively provide Display Output A and Display Output B in each of these display areas. These display areas need not be the same size and the emulator may provide the “main” display output to a larger one of the display areas.
In still other instances, the emulator may provide only one of the Display Outputs A and B to the screen of the hand-held computing system or hand-held communication device. The one output that is provided to the screen need not be the same throughout the game. Thus, for example, Display Output A may be provided at some times and Display Output B may output at other times.
In addition, the display area on the single display screen for Display Output A and the display area on the single display screen for Display Output B may be oriented differently (e.g., one horizontally oriented and the other vertically oriented). This may facilitate display of the two Display Outputs at the same time.
In other instances, one of the Display Outputs A and B may be provided to the screen while the other one is made to be accessible upon supplying a predetermined input or inputs to the hand-held computing system or hand-held communication device. Thus, for example, a player may provide a predetermined input (such as a key press or a touch screen input) to switch between one Display Output and the other.
In addition, as described above, one of the display screens of the example portable game system is touch-sensitive. If the display screen of the hand-held computing system or hand-held communication device is divided into two display areas, the emulator may configure one of the display areas to receive touch inputs during game play. Preferably, this one of the display areas would be the display area displaying the output that would be displayed on the touch screen of the example portable game system. Touch inputs to the other one of the display areas would preferably be ignored.
If the emulator outputs only one of Display Output A and Display Output B at a time to the single screen display of the PDA or hand-held communication device, touch inputs may be supplied by the player when the Display Output output to the touch screen of the example portable game system is displayed. If this screen is subsequently switched to the other of the two screens, touch inputs may be ignored.
Because there will likely be differences between the size of the touchscreen of the example portable game system and the size of the screen of the hand-held computing system or hand-held communication device, the emulator will need to appropriately scale the touch screen inputs.
An emulator of the example portable game systems may implement some or all of the following:
As one example, in the case where the software is written for execution on a platform using a specific processor and the host 1201 is a personal computer using a different (e.g., Intel) processor, emulator 1203 fetches one or a sequence of binary-image program instructions from storage medium 62 and converts these program instructions to one or more equivalent Intel binary-image program instructions. The emulator 1203 also fetches and/or generates graphics commands and audio commands and converts these commands into a format or formats that can be processed by hardware and/or software graphics and audio processing resources available on host 1201. As one example, emulator 1303 may convert these commands into commands that can be processed by specific graphics and/or or sound hardware of the host 1201 (e.g., using standard DirectX, OpenGL and/or sound APIs).
An emulator 1303 used to provide some or all of the features of the video game system described above may also be provided with a graphic user interface (GUI) that simplifies or automates the selection of various options and screen modes for games run using the emulator. In one example, such an emulator 1303 may further include enhanced functionality as compared with the host platform for which the software was originally intended.
A number of program modules including emulator 1303 may be stored on the hard disk 1211, removable magnetic disk 1215, optical disk 1219 and/or the ROM 1252 and/or the RAM 1254 of system memory 1205. Such program modules may include an operating system providing graphics and sound APIs, one or more application programs, other program modules, program data and game data. A user may enter commands and information into personal computer system 1201 through input devices such as a keyboard 1227, pointing device 1229, microphones, joysticks, game controllers, satellite dishes, scanners, or the like. These and other input devices can be connected to processing unit 1203 through a serial port interface 1231 that is coupled to system bus 1207, but may be connected by other interfaces, such as a parallel port, game port, Fire wire bus or a universal serial bus (USB). A monitor 1233 or other type of display device is also connected to system bus 1207 via an interface, such as a video adapter 1235.
System 1201 may also include a modem 1154 or other network interface means for establishing communications over a network 1152 such as the Internet. Modem 1154, which may be internal or external, is connected to system bus 123 via serial port interface 1231. A network interface 1156 may also be provided for allowing system 1201 to communicate with a remote computing device 1150 (e.g., another system 1201) via a local area network 1158 (or such communication may be via wide area network 1152 or other communications path such as dial-up or other communications means). System 1201 will typically include other peripheral output devices, such as printers and other standard peripheral devices.
In one example, video adapter 1235 may include a 3D graphics pipeline chip set providing fast 3D graphics rendering in response to 3D graphics commands issued based on a standard 3D graphics application programmer interface such as Microsoft's DirectX 7.0 or other version. A set of stereo loudspeakers 1237 is also connected to system bus 1207 via a sound generating interface such as a conventional “sound card” providing hardware and embedded software support for generating high quality stereophonic sound based on sound commands provided by bus 1207. These hardware capabilities allow system 1201 to provide sufficient graphics and sound speed performance to play software stored in storage medium 1305.
One or more speakers 1517 are connected to system bus 1507 via an audio interface 1519 to output sounds. A communication circuit 1521 is connected to system bus 1507 via a communications interface 1523 to permit communication with other devices. By way of illustration, communication circuit 1521 may, for example, be a modem and communications interface 1523 may be a serial port. Generally speaking, communication circuit 1521 may be configured for wired or wireless communication in accordance with any conventional communication protocol. A power supply 1525 provides power for the components of system 1201′.
The contents of any technical documents or patent documents referenced above are incorporated herein in their entirety.
As one embodiment of the present invention, the portable game machine having a hardware structure as shown in
While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2004-106874 | Mar 2004 | JP | national |
This application is a divisional of application Ser. No. 11/126,387 filed May 11, 2005 now U.S. Pat. No. 7,837,558, which is a continuation-in-part of application Ser. No. 11/111,985, filed Apr. 22, 2005, which is a continuation-in-part of application Ser. No. 10/921,957, filed on Aug. 20, 2004 now U.S. Pat. No. 7,786,997. The contents of each of these applications are incorporated herein in their entirety.
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| Child | 12949223 | US |
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| Child | 11126387 | US | |
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| Child | 11111985 | US |
