On the screen 50 are disposed first display electrodes X, second display electrodes Y and address electrodes A. The display electrodes Y are used as scan electrodes in addressing operation. The display electrodes Y and the address electrodes A form an electrode matrix for the addressing operation. A sustain driver 3 is connected to the display electrodes X while a scan driver 4 and a sustain driver 5 are connected to the display electrodes Y. Then, an address driver 6 is connected to the address electrodes A.
An image output device (not shown) such as a TV tuner or a computer outputs to the gas discharge display device 1 data R-DF, G-DF and B-DF together with a clock CLK for transferring pixels. The data R-DF, G-DF, and B-DF indicate gradation values (brightness) of three colors of R, G and B, respectively. Frame data DF is made up of the data R-DF, G-DF and B-DF.
Since the plasma display panel 2 is a binary light emission device, the gas discharge display device 1 displays a multi-gradation frame in the form of a plurality of two-gradation subframes. To that end, the gas discharge display device 1 includes a frame division circuit 7 for converting frame data DF into subframe data, a memory 8 for storing the subframe data temporarily and a data transfer circuit 9 for reading out predetermined subframe data from the memory 8 to send the same to the address driver 6.
The frame division circuit 7 converts the data R-DF, G-DF and B-DF into subframe data, respectively. The subframe data is a set of data in which one bit corresponds to one cell. A value of each bit indicates whether a cell is to be lit or not in the corresponding subframe, more specifically whether address discharges are necessary or not. In the illustrated example, the number of subframes is eleven. In the following description, the subframes from the leading subframe through the last subframe in display order are referred to as SF1, SF2, . . . SF10 and SF11 in order. The drawings conform to this.
In addressing operation performed on the respective subframes SF1-SF11, the data transfer circuit 9 reads out subframe data of three colors in the order corresponding to the color array in the screen 50 and serially outputs the subframe data thus read out to the address driver 6 in synchronism with scan of display lines.
Referring to
The addressing operation is write addressing operation in which address discharges are generated in cells to be lit for display of the corresponding subframe. Voltage for generating address discharges between the display electrode Y and the address electrode A is applied to cells to be lit. The address discharges form an appropriate amount of wall charge.
In the sustaining operation following the addressing operation, alternating voltage is applied at an electrode pair of the display electrode X and the display electrode Y. Display discharges are generated only in cells to be lit and an ultra violet ray emitted by a discharge gas excites the fluorescent materials 24, 25 and 26. Thereby, the fluorescent materials 24, 25 and 26 emit light. The light emission due to the display discharges is lighting.
For display of the leading subframe SF1 in display of each of frames, the gas discharge display device 1 having the structure described above causes a non-minimum brightness cell to be lit and causes at least one cell adjacent to the non-minimum brightness cell to be forcibly lit. Herein, the non-minimum brightness cell is, among the cells 51 making up the screen 50, a cell whose corresponding frame data DF has a value that is not a value indicating the minimum value (zero in general cases). In this embodiment, such characteristic operation is achieved by the frame division circuit 7. More specifically, the frame division circuit 7 generates subframe data indicating that a non-minimum brightness cell and cells adjacent thereto are caused to be lit in the subframe SF1.
The frame division circuit 7 includes a portion for converting frames into subframes, e.g., a conversion table 70 as shown in
In the conversion table 70, a combination of lit/non-lit (a lighting pattern) of eleven subframes SF1-SF11 is associated with, for example, each of gradation values (0-255) of frame data DF having 256 gradations. In
As is highlighted by circles in
According to the conversion based on the conversion table 70, in the case of display of the leading subframe SF1, non-minimum brightness cells corresponding to the gradation values “1”-“255” are caused to be lit. The lighting in the subframe SF1 prevents address discharge errors from occurring in the subframe SF2 and the subsequent subframes SF3-SF11 in non-minimum brightness cells corresponding to the gradation values “2”-“255”.
With the conversion table 70, the lighting of the non-minimum brightness cells in the subframe SF1 is not additional lighting for priming but genuine lighting in which gradation values of frame data DF are expressed. Thus, the display quality is not deteriorated at all.
Note that the number of subframes corresponding to one frame, brightness weight of each subframe, and weight array (the display order of subframes) are not limited to the exemplification. In particular, it is desirable that the weight array is an array effective in reducing pseudo contours and is not limited to the order of the weight.
The first example of such a lighting pattern modification can be achieved by a frame division circuit 7a having a structure shown in
The frame division circuit 7a includes a block 71 that converts frame data R-DF, G-DF and B-DF of three colors into subframe data R-SF1′, R-SF2 to R-SF11, G-SF′1, G-SF2 to G-SF11, B-SF1′, B-SF2 to B-SF11 in accordance with the conversion table 70, and a logic circuit 72 that performs a logical OR operation of the subframe data R-SF1′, G-SF1′ and B-SF1′ outputted by the block 71.
The subframe data of the subframes SF2 to SF11 outputted by the block 71 are written onto the memory 8 without any modifications. As for the leading subframe SF1, the output by the logic circuit 72 is written onto the memory 8 for three colors in common.
Note that the function of the block 71 may be achieved by a look-up table (LUP) or a logical operation circuit.
In a color array in which R, G and B are provided in this order from the left, in the case where an R cell in a target pixel is lit in isolation, a B cell in the left pixel is caused to be lit as shown in (b) of
An R cell in a target pixel is lit in the subframe SF1 in the case where the R cell is a non-minimum brightness cell or in the case where a G cell in the target pixel is not lit and a B cell in the left pixel is lit. A G cell in a target pixel is lit in the subframe SF1 only in the case where the G cell is a non-minimum brightness cell. A B cell in a target pixel is lit in the subframe SF1 in the case where the B cell is a non-minimum brightness cell, in the case where a G cell in the target pixel is lit, or in the case where an R cell in the right pixel is lit and a G cell in the target pixel is not lit.
In the second example, when subframe data of the subframe SF1 for B and R cells are determined, a case arises in which attention should be paid to lighting patterns of a plurality of pixels. Specifically, the cases of (b), (d) and (f) of
As shown in
The second example of such a lighting pattern modification can be achieved by a frame division circuit 7b having a structure shown in
The frame division circuit 7b includes the same block 71 as the example described above, and a logic circuit 73 that performs a logical OR operation of the subframe data R-SF1′, G-SF1′ and B-SF1′ outputted by the block 71.
As for the subframes SF2 to SF11, the subframe data outputted by the block 71 are written onto the memory 8 without any modifications. As for the leading subframe SF1, the output by the logic circuit 73 for each color is written onto the memory 8.
The logic circuit 73 includes five flip-flops for delaying data in order to generate subframe data of the subframe SF1 based on data of three pixels adjacent to one another. These flip-flops are so disposed that R is subjected to one-step data delay process and G and B are subjected to two-step data delay process. The first-stage input of the flip-flop for each color corresponds to the j+1 th pixel in
In the case where an R cell in a target pixel is lit in isolation, a B cell in the left pixel and a G cell in the target pixel are caused to be lit as shown in (b) of
An R cell in a target pixel is lit in the subframe SF1 in the case where the R cell is a non-minimum brightness cell, in the case where a G cell in the target pixel is lit, or in the case where a B cell in the left pixel is lit. A G cell in a target pixel is lit in the subframe SF1 in the case where the G cell is a non-minimum brightness cell, in the case where an R cell in the target pixel is lit, or in the case where a B cell in the target pixel is lit. A B cell in a target pixel is lit in the subframe SF1 in the case where the B cell is a non-minimum brightness cell, in the case where a G cell in the target pixel is lit, or in the case where an R cell in the right pixel is lit.
The third example of such a lighting pattern modification can be achieved by a frame division circuit 7c having a structure shown in
As for the subframes SF2 to SF11, the subframe data outputted by the block 71 are written onto the memory 8 without any modifications. As for the leading subframe SF1, the output by the logic circuit 74 for each color is written onto the memory 8.
The fourth example of such a lighting pattern modification can be achieved by a frame division circuit 7d having a structure shown in
As for the subframes SF2 to SF11, the subframe data outputted by the block 71 are written onto the memory 8 without any modifications. As for G, the subframe data of the subframe SF1′ outputted by the block 71 is written onto the memory 8 as subframe data of the subframe SF1 without any modifications. As for R and B, the output from the logical circuit 75 is written onto the memory 8 for each color as subframe data of the subframe SF1.
In the embodiments described above, the overall structure of the devices, the cell structures in the screen, the color arrays, the structures of the frame division circuit, the number of subframes corresponding to one frame, the brightness weight assigned to the subframe, the weight array, and the like may be changed as needed, in accordance with the subject matter of the present invention.
While example embodiments of the present invention have been shown and described, it will be understood that the present invention is not limited thereto, and that various changes and modifications may be made by those skilled in the art without departing from the scope of the invention as set forth in the appended claims and their equivalents.
Number | Date | Country | Kind |
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2006-247333 | Sep 2006 | JP | national |