Gate driver and repairing method thereof

Abstract

A gate driver and a repairing method are disclosed, wherein the gate driver is provided with one or more plurality of auxiliary stages that can substitute for a disabled stage, the gate driver including a shift register provided with a plurality of first output lines; at least three output repairing lines arranged across the first output lines; at least two clock transmission lines to transmit at least two clock pulses of different phases; at least one clock repairing line arranged across the clock transmission lines; and at least one auxiliary stage connected to the output repairing lines and to the at least one clock repairing line.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention.

In the drawings:

FIG. 1 is a block diagram illustrating a related art shift register;

FIG. 2 is a block diagram schematically illustrating a gate driver according to a first embodiment of the present invention;

FIG. 3 is a block diagram schematically illustrating a repairing method for the gate driver of FIG. 2 when a third stage of the gate driver is disabled;

FIG. 4 is a is a block diagram schematically illustrating a gate driver according to a second embodiment of the present invention;

FIG. 5 is block diagram schematically illustrating a repairing method of the gate driver of FIG. 4 when a third stage of the gate driver is disabled;

FIG. 6 is a block diagram schematically illustrating a gate driver according to a third embodiment of the present invention;

FIG. 7 is a block diagram schematically illustrating a repairing method of the gate driver of FIG. 6 when second and fourth stages of the gate driver are disabled;

FIG. 8 is a block diagram schematically illustrating a gate driver according to a fourth embodiment of the present invention;

FIG. 9 is a block diagram schematically illustrating a repairing method of the gate driver of FIG. 8 when second and fourth stages of the gate driver are disabled; and

FIG. 10 is a block diagram schematically illustrating a gate driver according to the fifth embodiment of the present invention.

Claims

1. A gate driver comprising: a shift register provided with a plurality of first output lines;at least three output repairing lines arranged across the first output lines;at least two clock transmission lines to transmit at least two clock pulses of different phases;at least one clock repairing line arranged across the clock transmission lines; andat least one auxiliary stage connected to the output repairing lines and to the at least one clock repairing line.

2. The gate driver of claim 1, wherein the shift register includes a plurality of stages in a sequence that are each supplied with at least one of the clock pulses transmitted through the clock transmission lines and that each outputs the supplied clock pulse as a corresponding scan pulse through a corresponding one of the first output lines.

3. The gate driver of claim 2, wherein one end of each first output line is connected to the stage and the other end thereof is connected to a gate line of an LCD panel.

4. The gate driver of claim 2, further comprising a second output line to supply the scan pulse output from an (n−1)th stage to an (n)th stage, wherein the second output line connects the first output line of the (n−1)th stage to the (n)th stage, and where n is a positive integer.

5. The gate driver of claim 4, further comprising a third output line that supplies the scan pulse output from the (n+1)th stage to the (n)th stage, wherein the third output line connects the first output line of the (n+1)th stage to the (n)th stage.

6. The gate driver of claim 2, wherein the auxiliary stage is positioned at one side of an outermost stage.

7. The gate driver of claim 2, wherein the auxiliary stage is positioned between adjacent stages.

8. The gate driver of claim 7, wherein the plurality of stages are divided into a plurality of groups of stages, and the auxiliary stage is provided between adjacent groups.

9. The gate driver of claim 2, wherein the auxiliary stage includes: a first input terminal connected to the clock repairing line;a second input terminal connected to the first output repairing line;a third input terminal connected to the second output repairing line; andan output terminal connected to the third output repairing line.

10. The gate driver of claim 9, wherein the first output repairing line is connected to the first output line of a stage prior in sequence to a predetermined stage; the second output repairing line is connected to the first output line of the predetermined stage; the third output repairing line is connected to the first output line of a stage subsequent in the sequence to the predetermined stage; and the clock repairing line is connected to one of the clock transmission lines that transmits the clock pulse to the predetermined stage.

11. The gate driver of claim 10, wherein the first output repairing line is connected to the first output line of the (n−1)th stage; the second output repairing line is connected to the first output line of the (n)th stage; the third output repairing line is connected to the first output line of the (n+1)th stage; and the clock repairing line is connected to one of the clock transmission lines that transmits the clock pulse to the (n)th stage, where n is an integer greater than 2.

12. The gate driver of claim 11, wherein the (n)th stage is electrically separated from the first output line; and the (n)th stage is electrically separated from one of the clock transmission line that supplies the clock pulse to the (n)th stage.

13. The gate driver of claim 2, wherein the auxiliary stage includes first and second auxiliary stages; wherein the first auxiliary stage is connected to one end of the first output repairing line, one end of the second output repairing line, one end of the third output repairing line, and the first clock repairing line; and the second auxiliary stage is connected to the other end of the first output repairing line, the other end of the second output repairing line, the other end of the third output repairing line, and the second clock repairing line.

14. The gate driver of claim 13, wherein the first output repairing line is connected to the first output line of a stage prior in sequence to a first predetermined stage, and is connected to the first output line of a stage prior in sequence to a second predetermined stage; the second output repairing line is connected to the first output line of the first predetermined stage, and is connected to the first output line of the second predetermined stage; the third output repairing line is connected to the first output line of the stage subsequent in sequence to the first predetermined stage, and is connected to the first output line of the stage subsequent in sequence to the second predetermined stage; the first clock repairing line is connected to one of the clock transmission lines that transmits the clock pulse to the first predetermined stage; the second clock repairing line is connected to one of the clock transmission line that transmits the clock pulse to the second predetermined stage; and wherein predetermined portions of the respective first, second and third output repairing lines are disconnected.

15. The gate driver of claim 14, wherein the first output repairing line is connected to the first output line of an (n−1)th stage and the first output line of an (m−1)th stage; the second output repairing line is connected to the first output line of the (n)th stage and the first output line of the (m)th stage; the third output repairing line is connected to a first output line of the (n+1)th stage and the first output line of a (m+1)th stage; the first clock repairing line is connected to one of the clock transmission lines that transmits the clock pulse to the (n)th stage; the second clock repairing line is connected to one of the clock transmission lines that transmits the clock pulse to the (m)th stage; the first output repairing line is electrically disconnected between the first output line of the (n−1)th stage and the first output line of the (m−1)th stage; the second output repairing line is electrically disconnected between the first output line of the (n)th stage and the first output line of the (m)th stage; and the third output repairing line is electrically disconnected to the first output line of the (n+1)th stage and the first output line of the (m+1)th stage, wherein n is an integer greater than 2 and m is an integer greater than n.

16. A gate driver comprising: a shift register provided with a plurality of first output lines;at least two output repairing lines arranged across the plurality of first output lines;at least two clock transmission lines to transmit at least two clock pulses provided with a phase difference;at least two clock repairing lines arranged across the clock transmission lines; andat least one auxiliary stage connected to the output repairing lines and clock repairing lines,wherein the shift register includes a plurality of stages in sequence each stage connected to one end of a corresponding first output line.

17. The gate driver of claim 16, wherein the auxiliary stage includes: a first input terminal connected to the first clock repairing line;a second input terminal connected to the second clock repairing line;a third input terminal connected to the first output repairing line; andan output terminal connected to the second output repairing line.

18. The gate driver of claim 17, wherein the first output repairing line is connected to the first output line of a stage prior in sequence to a predetermined stage; the second output repairing line is connected to the first output line of the predetermined stage; the first clock repairing line is connected to one of the clock transmission lines that transmits the clock pulse to the predetermined stage; and the second clock repairing line is connected to one of the clock transmission lines that transmits the clock pulse to the stage subsequent in sequence to the predetermined stage.

19. The gate driver of claim 18, wherein the first output repairing line is connected to the first output line of the (n−1)th stage; the second output repairing line is connected to the first output line of the (n)th stage; the first clock repairing line is connected to one of the clock transmission lines that transmits the clock pulse to the (n)th stage; and the second clock repairing line is connected to one of the clock transmission lines that transmits the clock pulse to the (n+1)th stage, where n is an integer greater than 2.

20. The gate driver of claim 19, wherein the (n)th stage is electrically separated from the first output line; and the (n)th stage is electrically separated from one of the clock transmission lines that supplies the clock pulse to the predetermined stage.

21. The gate driver of claim 16, wherein the auxiliary stage includes first and second auxiliary stages, wherein the first auxiliary stage is connected to one end of the first output repairing line, one end of the second output repairing line, the first clock repairing line, and the second clock repairing line; and the second auxiliary stage is connected to the other end of the first output repairing line, the other end of the second output repairing line, the third clock repairing line, and the fourth clock repairing line.

22. The gate driver of claim 21, wherein the first output repairing line is connected to the first output line of a stage prior in sequence to a first predetermined stage, and the first output line of the stage prior in sequence to a second predetermined stage; the second output repairing line is connected to the first output line of the first predetermined stage and the first output line of the second predetermined stage; the first clock repairing line is connected to one of the clock transmission lines that transmits the clock pulse to the first predetermined stage; the second clock repairing line is connected to one of the clock transmission lines that transmits the clock pulse to the stage subsequent in sequence to the first predetermined stage; the third clock repairing line is connected to one of the clock transmission line that transmits the clock pulse to the second predetermined stage; the fourth clock repairing line is connected to one of the clock transmission lines that transmits the clock pulse to the stage subsequent in sequence to the second predetermined stage; and predetermined portions of the respective first and second output repairing lines are disconnected.

23. The gate driver of claim 22, wherein the first output repairing line is connected to the first output line of the (n−1)th stage and the first output line of the (m−1)th stage; the second output repairing line is connected to the first output line of the (n)th stage and the first output line of the (m)th stage; the first clock repairing line is connected to one of the clock transmission lines that the transmits the clock pulse to the (n)th stage; the second clock repairing line is connected to one of the clock transmission lines that transmits the clock pulse to the (n+1)th stage; the third clock repairing line is connected to one of the clock transmission lines that transmits the clock pulse to the (m)th stage; the fourth clock repairing line is connected to one of the clock transmission lines that transmits the clock pulse to the (m+1)th stage; the first output repairing line is electrically disconnected between the first output line of the (n−1)th stage and the first output line of the (m−1)th stage; and the second output repairing line is electrically disconnected between the first output line of the (n)th stage and the first output line of the (m)th stage, where n is an integer greater than 2 and m is an integer greater than n.

24. The gate driver of claim 23, wherein the (n)th stage is electrically separated from the first output line of the (n)th stage; the (n)th stage is electrically separated from the clock transmission line that transmits the clock pulse to the (n)th stage; the (m)th stage is electrically separated from the first output line of the (m)th stage; and the (m)th stage is electrically separated from the clock transmission line that transmits the clock pulse to the (m)th stage.

25. A repairing method of a gate driver provided with a shift register including: a plurality of stages in a sequence each provided with output lines; first, second and third output repairing lines arranged across the output lines; at least two clock transmission lines to transmit at least two clock pulses provided with a phase difference therebetween; a clock repairing line arranged across the clock transmission lines; and an auxiliary stage connected to the first output repairing line, the second output repairing line, the third output repairing line and the clock repairing line, comprising: connecting the output line of the stage, prior in the sequence to a predetermined stage among the plurality of stages provided in the shift register, to the first output repairing line;connecting the output line of the predetermined stage to the second output repairing line;connecting the output line of the stage, subsequent in the sequence to the predetermined stage, to the third output repairing line; andconnecting the clock repairing line to one of the clock transmission lines that transmits the clock pulse to the predetermined stage.

26. The gate driver of claim 25, further comprising: electrically separating the predetermined stage from the output line of the predetermined stage; andelectrically separating the predetermined stage from one of the clock transmission lines that supplies the clock pulse to the predetermined stage.

27. A repairing method of a gate driver provided with a shift register including: a plurality of stages in a sequence each provided with a corresponding output line; first, second and third output repairing lines arranged across the output lines; at least two clock transmission lines to transmit at least two clock pulses provided with a phase difference therebetween; first and second clock repairing lines arranged across the clock transmission lines; a first auxiliary stage connected to one end of the first output repairing line, one end of the second output repairing line, one end of the third output repairing line, and the first clock repairing line; and a second auxiliary stage connected to the other end of the first output repairing line, the other end of the second output repairing line, the other end of the third output repairing line, and the second clock repairing line, comprising: connecting the first output repairing line to the output line of a stage prior in the sequence to a first predetermined stage among the plurality of stages provided in the shift register;connecting the second output repairing line to the output line of the first predetermined stage;connecting the third output repairing line to the output line of a stage subsequent in sequence to the first predetermined stage;connecting the first output repairing line to the output line of a stage prior in sequence to a second predetermined stage among the plurality of stages provided in the shift register;connecting the second output repairing line to the output line of the second predetermined stage;connecting the third output repairing line to the output line of a stage positioned subsequent in sequence to the second predetermined stage;connecting the first clock repairing line to one of the clock transmission lines that transmits the clock pulse to the first predetermined stage;connecting the second clock repairing line to one of the clock transmission lines that transmits the clock pulse to the second predetermined stage; anddisconnecting predetermined portions of the respective first, second and third output repairing lines.

28. The repairing method of claim 27, further comprising: electrically separating the first predetermined stage from the output line of the first predetermined stage;electrically separating the first predetermined stage from one of the clock transmission lines that supplies the clock pulse to the first stage;electrically separating the second predetermined stage from the output line of the second predetermined stage; andelectrically separating the second predetermined stage from one of the clock transmission lines that supplies the clock pulse to the second stage.

29. A repairing method of a gate driver provided with a shift register including: a plurality of stages in a sequence each provided with a corresponding output line; first and second output repairing lines arranged across the output lines; at least two clock transmission lines to transmit at least two clock pulses provided with a phase difference therebetween; first and second clock repairing lines arranged across the clock transmission lines; and an auxiliary stage connected to the first output repairing line, the second output repairing line, the first clock repairing line, and the second clock repairing line, comprising: connecting the first output repairing line to the output line of the stage positioned prior to a predetermined stage among the plurality of stages provided in the shift register;connecting the second output repairing line to the output line of the predetermined stage;connecting the first clock repairing line to one of the clock transmission lines that transmits the clock pulse to the predetermined stage; andconnecting the second clock repairing line to one of the clock transmission lines that transmits the clock pulse to the stage positioned following the predetermined stage.

30. The repairing method of claim 29, further comprising: electrically separating the predetermined stage from the output line of the predetermined stage; andelectrically separating the predetermined stage from the clock transmission line that transmits the clock pulse to the predetermined stage.

31. A repairing method of a gate driver provided with a shift register including: a plurality of stages in a sequence each provided with a corresponding output line; first and second output repairing lines arranged across the output lines; at least two clock transmission lines to transmit at least two clock pulses provided with a phase difference; first, second, third and fourth clock repairing lines arranged across the clock transmission lines; a first auxiliary stage connected to one end of the first output repairing line, one end of the second output repairing line, one end of the third output repairing line, the first clock repairing line, and the second clock repairing line; and a second auxiliary stage connected to the other end of the first output repairing line, the other end of the second output repairing line, the other end of the third output repairing line, the third clock repairing line, and the fourth clock repairing line, comprising: connecting the first output repairing line to the output line of the stage prior in the sequence to a first predetermined stage among the plurality of stages provided in the shift register;connecting the second output repairing line to the output line of the first predetermined stage;connecting the first output repairing line to the output line of the stage positioned prior in the sequence to a second predetermined stage among the plurality of stages provided in the shift register;connecting the second output repairing line to the output line of the second predetermined stage;connecting the first clock repairing line to one of the clock transmission lines that transmits the clock pulse to the first predetermined stage;connecting the second clock repairing line to one of the clock transmission lines that transmits the clock pulse to the stage positioned subsequent in the sequence to the first predetermined stage;connecting the third clock repairing line to one of the clock transmission lines that transmits the clock pulse to the second predetermined stage;connecting the fourth clock repairing line to one of the clock transmission lines that transmits the clock pulse to the stage positioned subsequent in the sequence to the second predetermined stage; anddisconnecting a predetermined portion of the first output repairing line and a predetermined portion of the second output repairing line.

32. The repairing method of claim 31, further comprising: electrically separating the first stage from the output line of the first predetermined stage;electrically separating the first stage from the clock transmission line that transmits the clock pulse to the first predetermined stage;electrically separating the second stage from the output line of the second predetermined stage; andelectrically separating the second stage from the clock transmission line that transmits the clock pulse to the second predetermined stage.