Claims
- 1. A gate turnoff thyristor which comprises a semiconductor body having at least four contiguous layers, namely, a first diffused layer of a first conductivity type, second layer lying contiguous to the first layer and having a second conductivity type, a third diffused layer lying contiguous to the second layer and having said first conductivity type, and a fourth diffused layer lying contiguous to the third layer and having said second conductivity type;
- an anode electrode mounted on said first layer;
- a gate electrode formed on said third layer; and
- a cathode electrode deposited on said fourth layer, and in which the following two equations are satisfied:
- .rho..multidot.V.sub.j /.rho..sub.sb .gtoreq.10.5(v.multidot.cm) and .rho..sub.sb .ltoreq.35(.OMEGA./ )
- where:
- .rho..sub.sb =sheet resistance (.OMEGA./ ) at the normal temperature of the third layer
- V.sub.j =backward withstanding voltage (V) at a PN junction between the third and fourth layers
- .rho.=specific resistance (.OMEGA..multidot.cm) of the second layer.
- 2. The GTO thyristor according to claim 1, wherein said fourth layer is of a mesa type.
- 3. The GTO thyristor according to claim 1, wherein said fourth layer is of a planar type.
- 4. The GTO thyristor according to claim 1, wherein said fourth layer is of a multi-emitter type.
- 5. The GTO thyristor according to claim 1, wherein said second layer comprises a first region lying contiguous to said first layer and having a high impurity concentration; and
- a second region lying contiguous to said third region and having a specific resistance .rho. at the normal temperature.
- 6. The GTO thyristor according to claim 1, wherein said second layer comprises a first region of high impurity concentration lying contiguous to said first layer and including a surface contacting the anode electrode;
- a second region lying contiguous to said third regions and having a specific resistance .rho. at the normal temperature; and
- said fourth layer has a surface contacting the cathode electrode.
- 7. The GTO thyristor according to claim 1, wherein said first layer is provided with a region of said second conductivity type whose surface contacts said anode electrode; and
- said third layer whose surface contacts said cathode electrode has a region of said second conductivity type contacting said gate electrode.
- 8. The GTO thyristor according to claim 1, wherein said first diffused layer is of a P conductivity type and acts as an anode layer, said second layer is of an N conductivity type and acts as a first base layer, said third diffused layer is of a P conductivity type and acts as a second base layer, and said fourth diffused layer is of an N conductivity type and acts as a cathode layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
52-24489 |
Mar 1977 |
JPX |
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CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation-in-part of our copending Ser. No. 792,398 now abandoned, filed Apr. 29, 1977, now abandoned and assigned to the same assignee as the parent application.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
3609476 |
Storm |
Sep 1971 |
|
Non-Patent Literature Citations (1)
Entry |
J. Shimizu et al., "High-Voltage High Power Gate-Assisted Turn-Off Thyristor for High Frequency Use," IEEE Trans. on Elec. Dev., vol. Ed. 23 #8, Aug. 1976, pp. 883-887. |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
792398 |
Apr 1977 |
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