GEIGER-MODE FOCAL PLANE ARRAY HAVING INCREASED TOLERANCE TO OPTICAL OVERSTRESS

Abstract

A GmAPD FPA having increased tolerance optical overstress includes a limit resistor that is monolithically integrated into each pixel in the FPA, and which limits the magnitude of the current entering the read out integrated circuit.

Description

FIELD OF THE INVENTION

This invention relates generally to Geiger-mode (Gm) avalanche photodiode (APD) focal plane arrays (FPAs) and, more particularly, to architectures and methods for increasing the optical overstress tolerance thereof.

BACKGROUND OF THE INVENTION

There is a potential for saturation or loss of functionality in GmAPD FPAs due to incoming high-intensity optical signals. These high-intensity signals can generate, in the GmAPD, excessively large currents, which are then injected into the read-out integrated circuit (ROIC). These large currents may result in corruption of data from the FPA or possibly result in damage to the sensor. It is desirable to avoid these effects, collectively referred to as “optical overstress,” through elements of the FPA design.

FIG. 1 depicts a circuit model for pixel 100 of a prior-art GmAPD FPA. In the context of a photodiode FPA, such as a GmAPD FPA, the term “pixel” collectively references (i) a single photodiode in the array thereof and (ii) a unit cell of the read-out integrated circuit, at a minimum. Thus, pixel 100 includes GmAPD 102 (of an array thereof referred to as a photodiode array or “PDA”) and ROIC unit cell 108.

The circuit model of the GmAPD 102 includes intrinsic instantaneous series resistance “R_S(t),” breakdown voltage “V_B,” diode capacitance “C_D,” and switch “S” to emulate the spontaneous avalanche breakdown process in the GmAPD. See, Haitz, R. H. “Model for the Electrical Behavior of a Microplasma” J. Appl. Phys. 35, 1370 (1964). ROIC unit cell 108 includes arm transistor 110, disarm transistor 112, and sense transistor 114.

GmAPD 102 is armed by externally applied voltage “V_HI,” with accompanying low-impedance load resistance R_L. Voltage V_HI is set as follows:

$\begin{array}{cc}{V}_{\mathrm{HI}}=V_B+\mathrm{excess}\mathrm{bias}{V}_{\mathrm{EX}}& \left(1\right)\end{array}$

• • where: V_EX<5 voltsThe source of the excess bias is disconnected after a user-defined “arm” time.

Referring now to FIGS. 2A and 2B, detection of an optical signal, and its corresponding avalanche, at time t=t₀, corresponds to the closing of switch S. At this time, voltage V between nodes 104 and 106 in FIG. 1 begins dropping from V_HI and current/begins increasing to I_A:

$\begin{array}{cc}{I}_A=\left(\left(V_{\mathrm{HI}}-V_B\right)/R_S\left(t\right)\right)& \left(2\right)\end{array}$

When sense transistor 114 in ROIC unit cell 108 detects that the voltage has dropped to quench voltage V_Q, disarm transistor 112 turns “on,” reducing the voltage across GmAPD 102 to V_LO, as depicted in FIG. 2A, where:

$\begin{array}{cc}{V}_{\mathrm{LO}}=V_{\mathrm{HI}}-5\mathrm{volts}& \left(3\right)\end{array}$

As the voltage is reduced below breakdown voltage V_B, switch S opens again and the current drops from steady-state value I₀ back to zero, as depicted in FIG. 2B. At this point, GmAPD 102 can be re-armed with arm transistor 110 after a user-defined hold-off time. This approach, called “active quenching,” enables much greater control over the functionality of a GmAPD in comparison with a “passive quenching” scheme, in which the disarming and re-arming occur automatically in accordance with behavior set by a single “quench” resistor in place of ROIC unit cell 108.

The initial spike in current/to I_A scales with optical intensity in the presence of a very large optical signal due to R_s(t) decreasing when an excess of free carriers are generated within the diode. High magnitudes of this peak current ultimately cause the issues attributed to “optical overstress” upon injection into ROIC unit cell 108. As this problem is relatively unique to GmAPD FPAs due to the high impedance necessary at the ROIC input for detection of avalanche events, to the inventors' knowledge, it has not been addressed in the prior art.

SUMMARY OF THE INVENTION

Embodiments of the invention provide a way to significantly increase the tolerance of a GmAPD FPA to optical overstress.

A first approach adopted by the present inventors to address the problem of high peak current was to shut down the power supply lines in the ROIC when high current is detected. This approach proved to be ineffective, however, due to the essentially instantaneous overstress impact of the current pulse (i.e. <<10 nanoseconds). The inventors then considered a second approach wherein the magnitude of the current is reduced before the current is injected into ROIC unit cell 108.

In accordance with the illustrative embodiment, one or more limit resistor(s) are monolithically integrated within each pixel of the GmAPD FPA. The inventors recognized that, based on certain considerations related to the architecture of their GmAPD arrays, the limit resistor(s) must be monolithically integrated. In some of such embodiments, the limit resistor(s) are integrated into the GmAPD of each pixel. In some other of such embodiments, the limit resistor(s) are integrated into the ROIC unit cell of each pixel. In some further embodiments, limit resistor(s) are integrated into both the GmAPD and the ROIC unit cell of each pixel.

As a consequence of the presence of the limit resistor(s) in accordance with the present teachings, when the switch S closes at time to, the voltage V drops more slowly than in the prior art (as depicted in FIG. 2A). Current still flows to the ROIC unit cell, but the total charge that is injected therein is discharged at more gradually, thereby reducing the peak current magnitude as compared to the prior art (as depicted in FIG. 2B). A further benefit of the embodiments of the invention over the initially attempted “shut-down” approach is that high-intensity input signals can still be detected and analyzed.

Some embodiments of the invention provide a GmAPD FPA comprising a plurality of pixels, each pixel comprising: an electrical circuit including a GmAPD, a unit cell of a ROIC, and a limit resistor, wherein the limit resistor is monolithically integrated in the pixel, and wherein the limit resistor limits a magnitude of a current entering the ROIC unit cell, wherein the current is generated by the GmAPD.

Some embodiments of the invention provide a GmAPD FPA comprising a plurality of pixels, each pixel comprising: a GmAPD having a limit resistor monolithically integrated therein, the limit resistor operable to limit a magnitude of a current generated by the GmAPD, and a unit cell of a ROIC that receives the current, as limited by the limit resistor, from the GmAPD.

Some embodiments of the invention provide a method for increasing the tolerance of a GmAPD FPA to optical overstress, the method comprising increasing, within each pixel of the GmAPD FPA, the series resistance of an electrical connection between the GmAPD and a unit cell of a ROIC.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts an electrical circuit model of a prior-art GmAPD FPA pixel.

FIG. 2A depicts the voltage-vs-time behavior of the pixel of FIG. 1 following an avalanche event.

FIG. 2B depicts the current-vs-time behavior of the pixel of FIG. 1 following an avalanche event.

FIG. 3A depicts an electrical circuit model of a GmAPD FPA pixel in accordance with a first embodiment of the present invention.

FIG. 3B depicts an electrical circuit model of a GmAPD FPA pixel in accordance with a second embodiment of the present invention.

FIG. 4A depicts a comparison of the voltage-vs-time behavior of the GmAPD FPA pixel of FIG. 1 and a GmAPD FPA pixel in accordance with the present teachings, following an avalanche event.

FIG. 4B depicts a comparison of the current-vs-time behavior of the GmAPD FPA pixel of FIG. 1 and a GmAPD FPA pixel in accordance with the present teachings, following an avalanche event.

FIG. 5 depicts a flow diagram of method for fabricating a GmAPD PDA pixel in accordance with the illustrative embodiment.

FIGS. 6A, 6C, and 6E depict cross-sectional views of a GmAPD PDA pixel in various stages of fabrication, in accordance with the illustrative embodiment.

FIGS. 6B, 6D, and 6F depict top views of a GmAPD PDA pixel in various stages of fabrication, in accordance with the illustrative embodiment.

FIG. 7 depicts a top view of a GmAPD FPA pixel at a stage of fabrication, and showing an alternative layout of a limit resistor.

DETAILED DESCRIPTION

Embodiments of the invention provide a GmAPD FPA having increased tolerance optical overstress. For the sake of clarity, the embodiments of the invention are depicted and described at the pixel level. Each GmAPD FPA pixel includes a GmAPD pixel and a unit cell of an ROIC. There is a 1:1 relationship between GmAPDs and unit cells of the ROIC. Each unit cell of the ROIC provides a digital readout of the avalanche events that occur within the associated GmAPD. It is within the capabilities of those skilled in the art to appropriately scale to the level of a GmAPD FPA.

FIG. 3A depicts a circuit model of GmAPD FPA pixel 300A, in accordance with an embodiment of the present invention. GmAPD FPA pixel 300A differs from prior-art GmAPD FPA pixel 100 in that the former includes limit resistor 316A. In this embodiment, limit resistor 316A is monolithically integrated into GmAPD 302 (as opposed to the ROIC unit cell). In an embodiment of a GmAPD FPA based on FIG. 3A, which will include a 2D array of pixels like that depicted in FIG. 3A, each such pixel will include limit resistor 316A that has been monolithically integrated within the GmAPD of the pixel.

In some embodiments in which limit resistor 316A is monolithically integrated in GmAPD 302, the limit resistor is a thin-film resistor that is patterned on the GmAPD from, for example, standard-production, high-resistivity NiCr and TaN thin films.

FIG. 3B depicts a circuit model of GmAPD FPA pixel 300B, in accordance with an embodiment of the present invention. Like GmAPD FPA pixel 300A, GmAPD FPA pixel 300B differs from prior-art GmAPD FPA pixel 100 in that pixel 300B includes limit resistor 316B. In this embodiment, however, limit resistor 316B is monolithically integrated into ROIC unit cell 306.

Thus, in both embodiments depicted, the limit resistor is: (a) located in the circuit between the GmAPD and the ROIC unit cell, and (b) monolithically integrated into the GmAPD FPA pixel.

FIGS. 4A and 4B depict a comparison of the electrical behavior of a prior-art GmAPD FPA pixel (see FIG. 1) and a GmAPD FPA pixel in accordance with the present teachings (e.g., see FIGS. 3A, 3B).

With reference to FIGS. 1, 3A, 3b, and 4A, upon closing of switch S at time to, the voltage V in a GmAPD FPA pixel in accordance with the present invention (dashed line) drops more slowly than a GmAPD FPA pixel of the prior art (solid line). As depicted in FIG. 4B, current/still flows to the ROIC, but the total charge injected into the ROIC (which is the area under each curve in FIG. 4B) is discharged at a more gradual pace, thereby reducing the peak current magnitude as compared to the prior art.

Because sense transistor 114 in the ROIC unit cell is a voltage threshold detector, the smaller current amplitudes generated in embodiments of the invention will not degrade the circuit's ability to detect avalanches. The primary performance trade-off to be considered is avoiding degradation of the FPA timing jitter performance associated with an increase in avalanche RC time constants induced by the presence of limit resistor 316A or 316B. This places an upper limit on useful values of the limit resistor of about 100 kOhms. The lower limit of resistance of the limit resistor, which is about 1 kOhm, is determined by the minimum value that reduces the peak current to an acceptable value.

Since the existing series resistance between the GmAPD anode and the ROIC input in an APD FPA is dominated by the contact resistance of the APD anode contact, which is about 100 ohms, the aforementioned resistance range of the limit resistor (i.e., about 1 kOhm to about 100 kOhms) is expected to yield, at minimum, a factor-of-ten improvement in optical-overload tolerance. At the same time, keeping the resistance in the aforementioned range will, as previously noted, avoid unacceptable levels of degradation in timing jitter performance.

As previously noted, in embodiments of the invention, the limit resistor is monolithically integrated into the GmAPD FPA pixel. A process for monolithically integrating the limit resistor into a GmAPD, such as to form GmAPD 301 (FIG. 3A), is disclosed in FIGS. 5 and 6A-6F and the accompanying description.

The fabrication operations germane to embodiments of the invention take place after epitaxial growth of the various layers (e.g., absorption layer, charge control layer, cap layer, etc.) composing an APD (hereinafter referred to in the disclosure and claims as the “APD device layers”), but before diffusing a dopant into the cap layer to form the active region of the APD. Conventional techniques are used for metal deposition, insulator deposition, patterning, etc.

Referring now to FIG. 5, in operation S501 of method 500, a layer providing electrical passivation (and also electrical insulation), referred to herein and the appended claims as a “passivation layer,” is deposited on the APD device layers. The passivation layer comprises, for example and without limitation, SiN_X, Al₂O₃, and SiO₂. In operation S502, an opening is patterned in the passivation layer and dopant is diffused through the opening, via standard techniques (photolithography/reactive ion etching, wet-etching, ion milling, sputtering, laser-assisted etching, etc.). It is within the capabilities of those skilled in the art to determine the size of the opening. If the material being doped is n-type semiconductor, the dopant will be a p-type dopant, such as zinc, cadmium, beryllium, and carbon. If the semiconductor layer is a p-type material, then the dopant will be an n-type dopant, such as sulfur or silicon. It is within the capabilities of those skilled in the art to appropriately dope the cap layer to provide an active region in the APD.

In operation S503, an n- or p-contact metal (dependent on device type) is deposited on a portion of the active region. As needed, additional “passivation” material is deposited to fill what remains of the opening formed in the passivation layer.

FIGS. 6A and 6B depict respective cross-sectional and top views of a nascent GmAPD at the completion of operation S503. At this point in the fabrication, the GmAPD includes substrate 620, APD device layers 622, active region 624, passivation layer 626, and contact 628.

In operation S504, a layer of metal, such as, without limitation, high resistivity NiCr or TaN, is deposited between the contact (i.e., contact 628) and a region in which a bond pad will be deposited. This layer of metal can be deposited, for example, via electron beam evaporation, or sputtering, and be patterned into a desired configuration using techniques known in the art. This layer of metal serves as the limit resistor.

In operation S505, additional metal is deposited in a location at which a bond pad is desired. This metal will partially (or wholly) overlap the metal serving as the limit resistor. The bond pad comprises, for example and without limitation, gold, aluminum, copper, and alloys thereof.

FIGS. 6C and 6D depict respective cross-sectional and top views of the nascent GmAPD at the completion of operation S505. At this stage of completion, the GmAPD includes limit resistor 630 and bond pad 632, in addition to substrate 620, APD device layers 622, active region 624, passivation layer 626, and contact 628.

In operation S506, a layer of electrical insulation is deposited over the APD. Materials suitable for use as the layer of electrical insulation include, for example and without limitation, BCB, SiO₂, SiN_x, and Al₂O₃. An opening is then formed around the bond pad to enable electrical contact between the GmAPD and the ROIC.

FIGS. 6E and 6F depict respective cross-sectional and top views of the GmAPD at the completion of operation S506, at which point the GmAPD, as modified to include the limit resistor, is complete. The GmAPD includes insulation layer 634, in addition to substrate 620, APD device layers 622, active region 624, passivation layer 626, and contact 628, limit resistor 630 and bond pad 632. Also depicted is electrical connection 636 from bond pad 632 to the ROIC.

FIG. 7 depicts resistor 730 having a serpentine shape, which is an alternative embodiment of limit resistor 630. Limit resistor 730 includes a greater number of resistor “squares” between the active region (i.e., active region 624) and bond pad 632, and thus presents greater electrical resistance. The excess of space available on the surface of the PDA is what enables the incorporation of additional resistor squares into the limit resistor. This approach, whereby additional resistor squares are added resulting in a serpentine (or other) shape, enables tuning the resistance of the limit resistor.

Monolithically integrating a limit resistor into an ROIC will necessarily proceed along a somewhat different path as a consequence of the structural differences between a GmAPD and a ROIC. In light of the present teachings, those skilled in the art will be able to adapt ROIC fabrication procedures to incorporate a limit resistor.

It is to be understood that the disclosure teaches just one example of the illustrative embodiment and that many variations of the invention can easily be devised by those skilled in the art after reading this disclosure and that the scope of the present invention is to be determined by the following claims.

Claims

1. A Geiger mode avalance photodiode (GmAPD) focal plane array (FPA) comprising a plurality of pixels, each pixel comprising: an electrical circuit including:a GmAPD;a unit cell of a read-out integrated circuit (ROIC unit cell); anda limit resistor, wherein the limit resistor is located in the electrical circuit between the GmAPD and the ROIC unit cell,wherein the ROIC unit cell comprises a plurality of transistors, and one end of the limit resistor is directly connected with one of the plurality of transistors,wherein the plurality of transistors provide active-quenching functionality for the GmAPD,wherein the limit resistor is configured to discharge total charge injected in the ROIC unit cell and reduce a peak magnitude of a current generated by the GmAPD, andwherein the limit resistor is monolithically integrated in the pixel.

2. The GmAPD FPA of claim 1, wherein the limit resistor is monolithically integrated with only the GmAPD of each pixel.

3. The GmAPD FPA of claim 1, wherein the limit resistor is monolithically integrated with only the ROIC of each pixel.

4. The GmAPD FPA of claim 1, wherein the limit resistor comprises a first limit resistor and a second limit resistor, the first limit resistor being monolithically integrated with the GmAPD of each pixel and the second limit resistor being monolithically integrated with the ROIC of each pixel.

5. The GmAPD FPA of claim 1, wherein the limit resistor is a thin-film resistor.

6. The GmAPD FPA of claim 1, wherein the limit resistor comprises materials selected from the group consisting of NiCr and TaN.

7. The GmAPD FPA of claim 1, wherein the limit resistor has a resistance in the range of about 1 kOhm to about 100 kOhms.

8. The GmAPD FPA of claim 1, wherein the GmAPD comprises: an active region formed within APD device layers;a passivation layer disposed on the APD device layers;an electrical contact formed on a portion of the active region;the limit resistor, wherein the limit resistor is disposed on the passivation layer and is in electrical communication with the electrical contact; anda bond pad formed on at least a portion of the limit resistor.

9. The GmAPD FPA of claim 8, wherein the limit resistor has a serpentine shape, and wherein the serpentine shape comprises a predetermined number of resistor squares between the active region and the bond pad.

10. The GmAPD FPA of claim 9, wherein the predetermined number of resistor squares corresponds to a desired tunable resistance of the limit resistor.

11. The GmAPD FPA of claim 1, wherein the plurality of transistors includes an active quenching circuit comprising: a sense transistor configured to receive an avalanche current from the GmAPD;an arm transistor; anda disarm transistor.

12. The GmAPD FPA of claim 11, wherein the limit resistor is electrically coupled between an electrical contact of the GmAPD and an input of the sense transistor in the active quenching circuit within the ROIC.

13. The GmAPD FPA of claim 11, wherein the active quenching circuit is configured to, in response to detecting the avalanche current, turn on the disarm transistor to reduce a voltage drop across the GmAPD.

14. The GmAPD FPA of claim 13, wherein the active quenching circuit is further configured to: detect a level of the voltage drop across the GmAPD falling to a level below a predetermined threshold voltage, andin response to detecting the voltage drop across the GmAPD, turn on the arm transistor to re-arm the GmAPD.

15. The GmAPD FPA of claim 14, wherein the predetermine threshold voltage corresponds to the breakdown voltage of the GmAPD.