Claims
- 1. A delay matched clock and data generator having data retiming element and a clock retiming element, each retiming element having the functionality of a two-input multiplexer and being connected and operated such that a level on an output(s) is controlled from data control inputs and a timing of transitions on the output(s) is controlled from timing control inputs, the data control inputs of each retiming element corresponding to data input(s) of the two-input multiplexer, and the timing control inputs of each retiming element corresponding to select input(s) of the two-input multiplexer, wherein a clock signal(s) is connected to the timing control inputs of the retiming elements, a data signal(s) is connected to a first data control input of the data retiming element, a delayed data signal(s) is connected to a second data control input of the data retiming element, and timing control signals are connected to the data control inputs of the clock retiming element.
- 2. The delay matched clock and data generator of claim 1, wherein the timing control signals are configured for stopping a clock signal on the output(s) at a low level.
- 3. The delay matched clock and data generator of claim 1, wherein the timing control inputs signals are configured for stopping a clock signal on the output(s) at a high level.
- 4. The delay matched clock and data generator of claim 1, wherein the timing control inputs signals are configured for generating a delay matched inverted signal.
- 5. The delay matched clock and data generator of claim 2, wherein the generator is operated for clock gating.
- 6. The delay matched clock and data generator of claim 2, wherein the generator is operated for polarity independent clock gating.
- 7. The delay matched clock and data generator of claim 1, wherein only a clock signal is sent from a transmitter to a receiver domain.
- 8. The delay matched clock and data generator of claim 7, wherein the timing control inputs signals are configured for stopping a clock signal at a low level.
- 9. The delay matched clock and data generator of claim 7, wherein the timing control inputs signals are configured for stopping a clock signal at a high level.
- 10. The delay matched clock and data generator of claim 7, wherein the timing control inputs signals are configured for generating a delay matched inverted signal.
- 11. The delay matched clock and data generator of claim 8, wherein the generator is operated for clock gating.
- 12. The delay matched clock and data generator of claim 8, wherein the generator is operated for polarity independent clock gating.
Priority Claims (1)
Number |
Date |
Country |
Kind |
9501608 |
May 1995 |
SE |
|
Parent Case Info
This application is a continuation of International Application No. PCT/SE96/00486, filed Apr. 15, 1996, which designates the United States.
US Referenced Citations (7)
Foreign Referenced Citations (2)
Number |
Date |
Country |
41 32 325 |
Apr 1993 |
DE |
356 042 |
Feb 1990 |
EP |
Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/SE96/00486 |
Apr 1996 |
US |
Child |
08/961411 |
|
US |