Generic maximum aposteriori probability decoder for use in software-defined radio systems

Abstract

A reconfigurable maximum a-posteriori probability (MAP) calculation circuit that reuses the arithmetic logic unit (ALU) hardware to calculate forward state metrics (alpha values), backward state metrics (beta values), and extrinsic information (lambda values) for the trellis associated with the MAP algorithm. The alpha, beta and lambda calculations may be performed by the same ALU hardware for both binary code (i.e., WCDMA mode) and duo-binary code (i.e, WiBro mode).

Description

TECHNICAL FIELD OF THE INVENTION

The present application relates generally to decoding algorithms and, more specifically, to a generic maximum a-posteriori probability (MAP) decoder for use in software-defined radio (SDR) systems.

BACKGROUND OF THE INVENTION

The maximum a-posteriori probability (MAP) algorithm is used in a number of coding schemes to improve the performance of communication systems. Maximum a-posteriori probability (MAP) decoders are used in, for example, turbo code-based radio frequency (RF) transceivers. Turbo coding is a powerful forward error correction (FEC) algorithm that achieves a coding gain close to the Shannon limit. Turbo encoders and turbo decoders have been adopted for use in the physical layers of a number of wireless standards, including WCDMA, CDMA2000, IEEE-802.16e (i.e., WiBro) and others. Thus, MAP decoders are implemented in, for example, WCDMA 8PCCC turbo decoders and in 802.16/Wibro CTC turbo decoders.

A software-defined radio (SDR) device uses reconfigurable hardware that may be programmed over-the-air to operate under different wireless standards. For example, an SDR transceiver in a wireless laptop computer or PDA may be configured by different software loads to operate in an IEEE-802.11x wireless network, a CDMA2000 wireless network, an OFDM/OFDMA wireless network, a GSM wireless network, or other types of networks. Many of these wireless standards require the use of turbo decoders or other decoders that are based on maximum a-posteriori probability (MAP) decoders.

However, conventional decoders have significant drawbacks with respect to SDR applications. Turbo decoders and other types of decoders are optimized for decoding under only one or two specific standards. Conventional designs use different MAP decoders to support each standard separately. For example, a MAP decoder calculates three values: alpha (α), beta (β), and lambda (λ). Normally, three distinct hardware blocks are used to calculate these values. This increases power consumption and uses a large amount of die space.

If an SDR device is required to support many wireless standards, more than one decoder must be implemented in the SDR device. This leads to a complex transceiver design that makes inefficient use of chip space and has high power dissipation. This also increases development cost and time-to-market (TTM). Additionally, some of the newer wireless standards operate at relatively high data rates (e.g., WiBro, HSPDA, and the like). A decoder that is optimized in terms of speed and power consumption for a low data rate standard is unlikely to be optimized in terms of speed and power consumption for a high data rate standard, and vice versa. Thus, conventional decoder designs are not suitable for use in SDR applications.

Therefore, there is a need in the art for an improved reconfigurable decoder for use in a software-defined radio (SDR) system. In particular, there is a need for a maximum a-posteriori probability (MAP) decoder that may be implemented in a reconfigurable decoder that operates under different wireless standards.

SUMMARY OF THE INVENTION

A reconfigurable maximum a-posteriori probability (MAP) calculation circuit is provided that reuses the same arithmetic logic unit (ALU) hardware to calculate forward state metrics (alpha values), backward state metrics (beta values), and extrinsic information (lambda values) for the trellis associated with the MAP algorithm. If the operands are prepared correctly, the alpha, beta and lambda calculations may be performed by the same ALU hardware for both binary code (WCDMA mode) and duo-binary code (WiBro mode).

According to an exemplary embodiment, the reconfigurable MAP calculation circuit comprises a reconfigurable maximum a-posteriori probability (MAP) calculation circuit for decoding duo-binary code data and binary code data. The reconfigurable MAP calculation circuit comprises a gamma calculation block for calculating a branch metric value for each branch of a trellis associated the MAP calculation circuit.

The gamma calculation block receives: 1) in duo-binary mode: i) duo-binary inputs (a, b) from a first time interval; ii) parity information generated from the duo-binary inputs (a,b); and iii) extrinsic information associated with previous nodes in the trellis; and 2) in binary mode: i) a first binary input x_i from a first time interval and a second binary input x_i+1 from a second time interval; ii) first parity information generated from the first binary input x_i and second parity information generated from the second binary input x_i+1; and iii) extrinsic information associated with previous nodes in the trellis.

The reconfigurable MAP calculation circuit further comprises a first arithmetic logic unit (ALU) stage for calculating alpha values for each node in the trellis in both duo-binary mode and binary mode, wherein the first ALU stage receives alpha values for previous nodes in the trellis and branch metric data from the gamma calculation block.

The first ALU stage is further capable of calculating beta values for each node in the trellis in both duo-binary mode and binary mode, wherein the first ALU stage receives beta values for previous nodes in the trellis and branch metric data from the gamma calculation block.

Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts:

FIG. 1 is a high-level block diagram of a CRISP device that may be used to implement a reconfigurable maximum a-posteriori probability (MAP) decoder;

FIG. 2 is a high-level block diagram of a reconfigurable processing system;

FIG. 3 is a high-level block diagram of a multi-standard software-defined radio (SDR) system that implements a reconfigurable maximum a-posteriori probability (MAP) decoder using at least one CRISP device;

FIG. 4A is a block diagram of a reconfigurable turbo decoder implemented in a CRISP according to the principles of the disclosure;

FIG. 4B is an exemplary trellis diagram for a WiBro wireless network;

FIG. 5A is a high-level block diagram illustrating a duobinary encoder according to an exemplary embodiment of the present disclosure;

FIG. 5B is a high-level block diagram illustrating abinary encoder according to an exemplary embodiment of the present disclosure;

FIG. 6 is a high-level block diagram illustrating a turbo decoder according to an exemplary embodiment of the present invention; and

FIGS. 7 and 8 are high-level block diagrams of a reconfigurable MAP decoder that operates in WiBro and WCDMA modes.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1 through 8, discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged processing system.

In the descriptions that follow, the reconfigurable maximum a-posteriori probability (MAP) decoder disclosed herein is implemented as part of a turbo decoder that provides a high degree of parallelism to support high data rate standards. The exemplary turbo decoder was disclosed in U.S. patent application Ser. No. 11/225,479, incorporated by reference above. However, it will be understood that the embodiment of the reconfigurable maximum a-posteriori probability (MAP) decoder in a turbo decoder is by way of illustration only and should not be construed to limit the scope of this disclosure. The reconfigurable MAP decoder disclosed herein may easily be adapted for use in decoders other that turbo decoders.

The reconfigurable MAP decoder and the reconfigurable turbo decoder support multimode operation for decoding in different communication standards, including WCDMA, CDMA2000, IEEE-802.16e (i.e., WiBro), among others. The disclosed MAP and turbo decoders also provide adaptability to support different data rates. WiBro and WCDMA/HSDPA operate at many different data rates. The disclosed MAP and turbo decoder architectures are optimized not only for the maximum data rates but also for different ranges of data rate.

In one embodiment of the disclosure, the reconfigurable MAP and turbo decoders described herein may be implemented using a context-based operation reconfigurable instruction set processor (CRISP) device. CRISP devices are described in detail in U.S. patent application Ser. No. 11/123,313, which was incorporated by reference above.

FIG. 1 is a high-level block diagram of context-based operation reconfigurable instruction set processor (CRISP) 100, which may be used to implement a turbo decoder containing a MAP decoder according to the principles of the present disclosure. CRISP 100 comprises memory 110, programmable data path circuitry 120, programmable finite state machine 130, and optional program memory 140. A context is a group of instructions of a data processor that are related to a particular function or application, such as turbo decoding instructions. As described in U.S. patent application Ser. No. 11/123,313, CRISP 100 implements only a subset of context-related instructions in an optimum manner.

Context-based operation reconfigurable instruction set processor (CRISP) 100 defines the generic hardware block that usually consists of higher level hardware processor blocks. The principle advantage to CRISP 100 is that CRISP 100 breaks down the required application into two main domains, a control domain and a data path domain, and optimizes each domain separately. By performing turbo decoding in CRISP 100, the disclosed turbo decoder reduces the problems related to flexibility and power consumption that affect conventional turbo decoders.

The control domain is implemented by programmable finite state machine 130, which may comprise a DSP, an MCU or another prior art device. Programmable FSM 130 is configured by reconfiguration bits received from an external controller (not shown). Programmable FSM 130 may execute a program stored in associated optional program memory 140. The program may be stored in program memory 140 via the DATA line from an external controller (not shown). Memory 110 is used to store application data used by data path circuitry 120.

Programmable data path circuitry 120 is divided into sets of building blocks that perform particular functions (e.g., registers, multiplexers, multipliers, and the like). Each of the building blocks is both reconfigurable and programmable to allow maximum flexibility. The division of programmable data path circuitry 120 into functional blocks depends on the level of reconfigurability and programmability required for a particular application.

Since different contexts are implemented by separate CRISP devices that work independently of other CRISP devices, implementing a turbo decoder using one or more CRISP devices provides an efficient power management scheme that is able to shut down a CRISP when the CRISP is not required. This assures that only the CRISPs that are needed at a given time are active, while other idle CRISPs do not consume significant power.

FIG. 2 is a high-level block diagram of reconfigurable processing system 200 according to one embodiment of the present disclosure. Reconfigurable processing system 200 comprises N context-based operation reconfigurable instruction set processors (CRISPs), including exemplary CRISPs 100a, 100b, and 100c, which are arbitrarily labeled CRISP 1, CRISP 2 and CRISP N. Reconfigurable processing system 200 further comprises real-time sequencer 210, sequence program memory 220, programmable interconnect fabric 230, and buffers 240 and 245.

Reconfiguration bits may be loaded into CRISPs 100a, 100b, and 100c from the CONTROL line via real-time sequencer 210 and buffer 240. A control program may also be loaded into sequence program memory 220 from the CONTROL line via buffer 240. Real-time sequencer 210 sequences the contexts to be executed by each one of CRISPs 100a-c by retrieving program instructions from program memory 220 and sending reconfiguration bits to CRISPs 100a-c. In an exemplary embodiment, real-time sequencer 210 may comprise a stack processor, which is suitable to operate as a real-time scheduler due to its low latency and simplicity.

Reconfigurable interconnect fabric 230 provides connectivity between each one of CRISPs 100a-c and an external DATA bus via bi-directional buffer 245. In an exemplary embodiment of the present disclosure, each one of CRISPs 100a-c may act as a master of reconfigurable interconnect fabric 230 and may initiate address access. The bus arbiter for reconfigurable interconnect fabric 230 may be internal to real-time sequencer 210.

In an exemplary embodiment, reconfigurable processing system 200 may be, for example, a cell phone or a similar wireless device, or a data processor for use in a laptop computer. In a wireless device embodiment based on a software-defined radio (SDR) architecture, each one of CRISPs 100a-c is responsible for executing a subset of context-related instructions that are associated with a particular reconfigurable function. For example, CRISP 100a may be configured to execute context-related instructions that process CDMA baseband signals or OFDMA baseband signals. CRISP 100b may be configured to execute context-related instructions that act as a memory controller. CRISP 100c may be configured to execute context-related instructions that perform turbo decoding or Viterbi decoding.

Since CRISP devices are largely independent and may be run simultaneously, a turbo decoder implemented using one or more CRISP devices has the performance advantage of parallelism without incurring the full power penalty associated with running parallel operations. The loose coupling and independence of CRISP devices allows them to be configured for different systems and functions that may be shut down separately.

FIG. 3 is a high-level block diagram of multi-standard software-defined radio (SDR) system 300, which implements a reconfigurable turbo decoder using a CRISP device. SDR system 300 may comprise a wireless terminal (or mobile station, subscriber station, etc.) that accesses a wireless network, such as, for example, a GSM or CDMA cellular telephone, a PDA with WCDMA, IEEE-802.11x, OFDM/OFDMA capabilities, or the like.

Multi-standard SDR system 300 comprises baseband subsystem 301, applications subsystem 302, memory interface (IF) and peripherals subsystem 365, main control unit (MCU) 370, memory 375, and interconnect 380. MCU 370 may comprise, for example, a conventional microcontroller or a microprocessor (e.g., x86, ARM, RISC, DSP, etc.). Memory IF and peripherals subsystem 365 may connect SDR system 300 to an external memory (not shown) and to external peripherals (not shown). Memory 375 stores data from other components in SDR system 300 and from external devices (not shown). For example, memory 375 may store a stream of incoming data samples associated with a down-converted signal generated by radio frequency (RF) transceiver 398 and antenna 399 associated with SDR system 300. Interconnect 380 acts as a system bus that provides data transfer between subsystems 301 and 302, memory IF and peripherals subsystem 365, MCU 370, and memory 375.

Baseband subsystem 301 comprises real-time (RT) sequencer 305, memory 310, baseband DSP subsystem 315, interconnect 325, and a plurality of special purpose context-based operation instruction set processors (CRISPs), including transform CRISP 100d, chip rate CRISP 100e, symbol rate CRISP 100f, and bit manipulation unit (BMU) CRISP 100g. By way of example, transform CRISP 100d may implement a Fast Fourier Transform (FFT) function, chip rate CRISP 100e may implement a correlation function for a CDMA signal, and symbol rate CRISP 100f may implement a turbo decoder function or a Viterbi decoder function.

In such an exemplary embodiment, transform CRISP 100d may receive samples of an intermediate frequency (IF) signal stored in memory 375 and perform an FFT function that generates a sequence of chip samples at a baseband rate. Next, chip rate CRISP 100e receives the chip samples from transform CRISP 100d and performs a correlation function that generates a sequence of data symbols. Next, symbol rate CRISP 100f receives the symbol data from chip rate CRISP 100e and performs turbo decoding or Viterbi decoding to recover the baseband user data. The baseband user data may then be used by applications subsystem 302.

In an exemplary embodiment of the present disclosure, symbol rate CRISP 100f may comprise two or more CRISPs that operate in parallel. Also, by way of example, BMU CRISP 100g may implement such functions as variable length coding, cyclic redundancy check (CRC), convolutional encoding, and the like. Interconnect 325 acts as a system bus that provides data transfer between RT sequencer 305, memory 310, baseband DSP subsystem 315 and CRISPs 100d -100g.

Applications subsystem 302 comprises real-time (RT) sequencer 330, memory 335, multimedia DSP subsystem 340, interconnect 345, and multimedia macro-CRISP 350. Multimedia macro-CRISP 350 comprises a plurality of special purpose context-based operation instruction set processors, including MPEG-4/H.264 CRISP 550h, transform CRISP 550i, and BMU CRISP 100j. In an exemplary embodiment of the disclosure, MPEG-4/H.264 CRISP 550h performs motion estimation functions and transform CRISP 100h performs a discrete cosine transform (DCT) function. Interconnect 380 provides data transfer between RT sequencer 330, memory 335, multimedia DSP subsystem 340, and multimedia macro-CRISP 350.

In the embodiment in FIG. 3, the use of CRISP devices enables applications subsystem 302 of multi-standard SDR system 300 to be reconfigured to support multiple video standards with multiple profiles and sizes. Additionally, the use of CRISP devices enables baseband subsystem 301 of multi-standard SDR system 300 to be reconfigured to support multiple air interface standards. Thus, SDR system 300 is able to operate in different types of wireless networks (e.g., CDMA, GSM, 802.11x, etc.) and can execute different types of video and audio formats. However, the use of CRISPS according to the principles of the present disclosure enables SDR system 300 to perform these functions with much lower power consumption than conventional wireless devices having comparable capabilities.

FIG. 4A is a block diagram of a reconfigurable turbo decoder implemented in CRISP 100f according to the principles of the disclosure. Turbo decoder CRISP 100f comprises program memory 405, configuration register files 410, address generator 415, communication switch 420, processing units 430a-430d, input data memories 440a-440d, extrinsic information memories 445a-445d, and internal bus 490. Each one of processing units 430a-430d comprises a control state machine (SM), a maximum a-posteriori probability (MAP) datapath, a cache, and control register files. By way of example, processing unit 430 comprises control state machine 431a, MAP datapath 432a, cache 433a, and control register files 434a. Although four processing units 430 are illustrated in FIG. 4A, this is by way of example only. Other embodiments of turbo decoder CRISP 100f may implement less than four processing units 430 or more than four processing units 430.

A conventional MAP turbo decoder architecture generally comprises two primary functional blocks: i) soft-input, soft-output (SISO) stages that implement an a-posteriori probability (APP) algorithm; and ii) an interleaver/deinterleaver that scrambles the data according to the interleaving rules followed by the encoder in the transmitting device. Other blocks are required for the implementation of the decoder, such as a RAM (random-access memory) for storing data from each iteration of the decoder. Turbo decoder CRISP 100f includes all the building blocks of a conventional MAP turbo decoder. In an exemplary embodiment, each one of MAP datapaths 432a-432d implements a sliding window MAP algorithm. However, alternate embodiments of turbo decoder CRISP 100f may implement non-sliding window MAP algorithms.

In turbo decoder CRISP 100f, MAP datapaths 432a, 432b, 432c and 432d temporarily store the values of α (alpha), β (beta), and λ (lambda) in caches 433a, 433b, 433c, and 433d. The extrinsic information (i.e., the λ values) from each iteration for each decoding block is stored in extrinsic information memories 445a, 445b, 445c and 445d via communication switch 420. In an exemplary embodiment, MCU 370 loads a configuration program and configuration data into turbo decoder CRISP 100f via an external system bus (i.e., interconnect 325). The configuration program is stored in program memory 405. MCU 370 loads the configuration data into configuration register files 410 and control register files 434a-434d in order to initialize the register files. Configuration register files 410 and control register files 434a-434d are used to control which processing units 430a-430d, input data memories 440a-440d, and extrinsic information memories 445a-445d are used in an application. Configuration register files 410 provide enable (EN) signals to control processing units 430, input data memories 440, and extrinsic information memories 445. Turbo decoder CRISP 100f reads input data samples and writes decoded output data via the system bus (i.e., interconnect 325).

In order to achieve high decoding rates, turbo decoder CRISP 100f implements N parallel processing units 430a-430d. In this example, N=4. Processing units 430a-430d are independent and identical to each other. Each one of processing units 430a-430d is capable of connecting to each one of input data memories 440a-440d and extrinsic information memories 445a-445d via communication switch 420. For higher data rate standards, all of processing units 430a-430d may operate simultaneously and in parallel. For lower data rate standards, one or more of processing units 430a-430d may be set to a sleep mode (i.e., deactivated or disabled) in order to reduce power consumption.

As noted above, each one of processing units 430a-430d comprises control state machine 431, MAP datapath 432, cache 433 and control register files 434. In an exemplary embodiment of turbo decoder CRISP 100f, each processing unit 430 processes two soft input data samples at a time. The two soft input data samples correspond to two data symbols. In an exemplary embodiment, each soft input data sample may comprise 8 bits. MAP datapath 432 performs both forward and backward recursions over the trellis. During the forward recursion and optionally also during the backward recursion, both the input symbol and the extrinsic (λ) information must be accessed to compute the branch metric, γ (gamma). In order to reduce memory access power consumption, the γ value may be computed and stored in cache 433 in each processing unit 430. If the values of α, β, and λ are not calculated simultaneously, the α value may also be stored in cache 430 to reduce data movement and power consumption.

MAP datapath 432 may compute the α, β, and λ values in parallel or in consecutive (or sequential) order. Parallel execution is faster, but requires more die space and power consumption. Consecutive processing incurs longer delays, but requires less die space and less power consumption. In an exemplary embodiment, each one of MAP datapaths 430a-430d computes the α, β, and λ values sequentially. Control state machine 431 decodes instructions from program memory received via internal bus 490 and controls the overall operation and configuration of processing unit 430. Since turbo decoder CRISP 100f may compute large instruction loops, control state machine 431 may use a hardware loop to reduce overhead and power consumption.

There are eight memory blocks in turbo decoder CRISP 100f: four input data memories 440a that hold the input data (or symbol) samples and four extrinsic information memories 445 that hold the extrinsic information (i.e., λ values) generated in each half iteration of the turbo decoder. The eight memory blocks are divided into four groups. Each memory group includes one input data memory 440 and one extrinsic information memory 445. By way of example, input data memory 440a and extrinsic information memory 445a form a first memory group, input data memory 440b and extrinsic information memory 445b form a second memory group, and so forth.

Each one of processing units 430a-430d reads and writes to one memory group at a time. Each one of processing units 430a-430d is capable of writing to each one of the memory groups. Thus, none of the memory groups is dedicated to a specific processing unit 430. For example, processing unit 430a may be connected by communication switch 420 to a first memory group (e.g., memories 440a and 445a) during one memory cycle and may read from or write to another memory group (e.g., memories 440c and 445c) during another memory cycle.

Communication switch 420 dynamically controls the connections between processing units 430a-430d and the memory groups comprised of memories 440a-440d and memories 445a-445d. The connection order or pattern is determined by the operation of address generator 415. Thus, communication switch 420 performs the interleaver and deinterleaver operations for a MAP decoder. In one embodiment of the disclosure, address generator 415 may be implemented by a memory. In such an embodiment, the external control DSP/MCU, such as MCU 370, pre-computes offline the interleaver pattern of the turbo decoder and writes the interleaver pattern to the memory of address generator 415 during an initialization phase. In another embodiment of the disclosure, address generator 415 may be designed to generate the interleaver pattern in real time. According to the principles of the disclosure, MAP datapaths 432a-d are reconfigurable devices that may be modified to operate in turbo decoders or other types of decoders and may be modified to operate under different RF protocols. Thus, MAP datapaths 432a-d provide a generic architecture to support not only α (alpha), β (beta), λ (lambda), and γ (gamma) calculations, but also to support different communication systems that use MAP decoders.

A MAP algorithm may be represented by a trellis. Different communication systems, such as WCDMA, WiBro, or the like, use different trellises. FIG. 4B illustrates exemplary trellis 499 for a WiBro wireless network that may be implemented by reconfigurable MAP datapaths 432a-d. Inside trellis 499 in FIG. 4B, alpha, beta and lambda are calculated in either the forward direction or the backward direction. It is noted that there are eight states in trellis 499 and that there are four paths leading from a state at time t to a state at time t+1. This means there are 32 possible paths between states in trellis 499.

As is well known, a conventional turbo encoder uses two constituent encoders. A first encoder receives an original bit stream and generates a first parity bit stream. A second encoder receives an interleaved copy of the original bit stream and generates a second parity bit stream. The data transmitted by the turbo encoder comprises the original bit stream, the first parity bits from the first encoder, and the second parity bits from the second encoder.

FIG. 5A is a high-level block diagram illustrating duobinary encoder 500 according to an exemplary embodiment of the present disclosure. Duobinary encoder 500 comprises recursive systematic code (RSC) encoders 505 and 510 and interleaver 515. In a duo-binary encoder (i.e., WiBro mode), a first sequence of the inputs a and b is applied to RSC encoder 505 and a second, interleaved sequence of the inputs a and b is applied to RSC encoder 510. The first encoder (RSC encoder 505) outputs the first parity bit stream (y, w), and the second encoder (RSC encoder 510) outputs the second parity bit stream (y′, w′).

FIG. 5B is a high-level block diagram illustrating binary encoder 550 according to an exemplary embodiment of the present disclosure. Binary encoder 550 comprises recursive systematic code (RSC) encoders 555 and 560 and interleaver 565. In a binary turbo encoder (i.e., WCDMA mode), a first sequence of input X_k is applied to RSC encoder 555 and a second, interleaved sequence of the input X_k is applied to RSC encoder 560. The first encoder (RSC encoder 555) outputs the first parity bit stream y_k and the second encoder (RSC encoder 560) outputs the second parity bit stream y′_k.

FIG. 6 is a high-level block diagram illustrating turbo decoder 600 according to an exemplary embodiment of the present invention. Each one of processing units 430a-430d implements a turbo decoder similar to turbo decoder 600. Turbo decoder 600 comprises maximum a-posterior probability (MAP) decoder block 610, maximum a-posterior probability (MAP) decoder block 620, and deinterleaver block 640. MAP decoders 610 and 620 operate in an iterative manner. MAP decoder 620 generates a new sequence of soft decision outputs that are fed back to MAP decoder 610 via deinterleaver block 640. This process may be iterated several times to increase the reliability of the decoded sequence.

MAP decoder block 610 receives data samples (soft values) from the demodulator corresponding to the non-interleaved (non-I/L) original data bits (e.g., x_k or (a,b) from FIGS. 5A and 5B), the first parity bits (e.g., y_k or (y,w) from FIGS. 5A and 5B) processed by the first encoder (505 or 555) in the transmitter, and the input L_a, which is the extrinsic (λ) information from MAP decoder 620. MAP decoder block 610 uses the original data bits and the first parity bits to estimate the probability, or log likelihood ratio (LLR), that the value of each original data bit is a Logic 1 or a Logic 0. MAP decoder block 620 receives data samples (soft values) from the demodulator corresponding to the interleaved (I/L) original data bits (e.g., interleaved X_k or interleaved (a,b) from FIGS. 5A and 5B), the second parity bits (e.g., y′_k or (y′,w′) from FIGS. 5A and 5B) processed by the second encoder (510 or 560), and the probability estimates (LR) from MAP decoder block 610.

The process of decoding by MAP decoder blocks 610 and 620 comprises one iteration of turbo decoder 600. Turbo decoder 600 may perform a fixed number of iterations or half iterations or may perform iterations until some external mechanism determines that additional iterations will not improve the bit error rate (BER) for a particular data frame. A hard decision is then made on the last soft outputs to determine the original data bits.

As is well known, a MAP algorithm is a trellis decoding algorithm, similar to the Viterbi algorithm. The MAP algorithm within the two decoder blocks operates on soft inputs (i.e., the demodulator outputs and the probability estimates) and produces soft outputs. The following description summarizes the MAP algorithm computations performed by one iteration of one decoder block. It should be noted that the exemplary turbo decoder processes two (2) input symbols at a time. In the case of duo-binary code (i.e., WiBro mode), the two input symbols to turbo decoder 600 are a, b, y, w, y′ and w′ from a single time sample. In the case of binary code (i.e., WCDMA mode), the inputs to the turbo decoder are x₁, y₁, and y′₁, from a first time sample and x₂, y₂, and y′₂ from a second time sample. Processing two input symbols at a time requires a radix-4 trellis mechanism, as shown in FIG. 4B.

In a first step, a conventional MAP algorithm may compute and store branch metrics, called gamma (or γ) values, for all branches of the trellis. Alternatively, in the first step, the MAP algorithm may perform an “on-the-fly” calculation of the branch metric for each alpha stage or beta stage. The branch metrics are the exponentials of the negatives of the distances between the hard encoder values and the soft received values from the demodulator, divided by the channel noise variance, multiplied by the probability estimate from the previous decoder. In the logarithmic domain, the branch metric (gamma) values are merely the summation of the above parameters.

In a second step, the conventional MAP algorithm performs a forward recursion on the trellis. The forward recursion computes an alpha (or α) value for each node in the trellis. The α value is the sum of: i) the previous α value times the branch metric along one branch from a previous node, ii) the previous α value times the branch metric along another branch from a previous node, iii) the previous α value times the branch metric along one branch from a another previous node, and iv) the previous a value times the branch metric along another branch from a previous node. In the logarithmic domain, the alpha values are the summation of the above parameters and finding the survivor between the four candidates, as described below.

In a third step, the conventional MAP algorithm performs a backward recursion on the trellis. The backward recursion computes a beta (or β) value for each node in the trellis. The β values are computed in a manner similar to the α values, except that the backward recursion starts at the end of the trellis and progresses in the reverse direction.

In a fourth step, the conventional MAP algorithm computes the log likelihood ratio (LLR), or λ (lambda) value, for each time t. In the case of a binary code, this value is the sum of the products of the α, β, and γ values for each branch at time t that is associated with a Logic 1 value in the encoder, divided by the sum of the products of the α, β, and λ values for each branch at time t that is associated with a Logic 0 value in the encoder. In the case of a duo-binary code, there are four (4) λ (lambda) values for each time t: λ00, λ01, λ10 and λ11. The λ00 value is the sum of the products of the α, β, and γ values for each branch at time t that is associated with a Logic “00” value in the encoder. The λ01 value is the sum of the products of the α, β, and γ values for each branch at time t that is associated with a Logic “01” value in the encoder. The λ10 value is the sum of the products of the α, β, and γ values for each branch at time t that is associated with a Logic “10” value in the encoder. The λ11 value is the sum of the products of the α, β, and γ values for each branch at time t that is associated with a Logic “11” value in the encoder.

Usually all lambdas are normalized by the L00 value and only three (3) lambdas—L01, L10, and L11—are saved and used for the next half iteration. Finally, the conventional MAP algorithm computes the extrinsic information that is to be sent to the next decoder in the iteration sequence. For binary code (i.e., WCDMA), the extrinsic information is the LLR value minus the input probability estimate. The computations described above are repeated in each iteration by each of the two decoder blocks. After all iterations are completed, decoded information bits may be detected by making a decision on each data bit or data pair. Alternatively, in both codes, the LLR values may be output to an external device that makes a decision on each data bit or data pair.

According to the principles of the present disclosure, the soft decisions are obtained using a MAP algorithm that is similar to the Viterbi algorithm with two major modifications. First, unlike the Viterbi algorithm, the trellis is swept twice—once in the forward direction and once in the reverse direction. Also, the add-compare-select (ACS) operation is replaced by the more complex max* operation (explained below).

The Log-Likelihood Ratio (LLR)—The binary values, Logic 0 and Logic 1, are represented by amplitudes (or signal levels) of +1 and −1, respectively, which are transferred to the receiver via a noisy channel. In the receiving device, the values of the soft symbols are distributed with characteristics depending on the channel. Without loss of generality, the descriptions that follow discuss the case of an additive white Gaussian noise (AWGN) channel. The input symbols into the decoder are normally distributed with centers around values +1 and −1.

The standard deviation, σ, is given by: $\begin{array}{cc}{\sigma }^2=0.5{\left(\frac{E_b}{N_0}\right)}^{-1},& \left[\mathrm{Eqn}.1\right]\end{array}$ where E_b is the energy per bit and N₀ is the channel noise. Hereafter, the following notations are used: i) the value, {right arrow over (Y)}, is a received sequence that includes systematic and parity information; and ii) Y_k≡(X_k,Y_k⁰,Y_k¹ . . . ) is the noisy version of the unperturbed sequence (X_k,y_k⁰,y_k¹ . . . ).

The decoder decides whether a soft input bit represents a Logic 1 or Logic 0 based on a maximum a-posteriori likelihood process. If L₂>L₁, the received bit, X_k, is decoded as d_k=+1. Otherwise, the received bit, X_k, is decoded as d_k=−1. For a received sequence, {right arrow over (Y)}, an observation, X_k, at the kth time interval is decoded as a Logic 1 if the a-posteriori likelihood, P(d_k=−1|{right arrow over (Y)}), exceeds the a-posteriori likelihood, P(d_k=+1|{right arrow over (Y)}). This may be expressed as: $\begin{array}{cc}\frac{P\left(d_k=+1\text{|}\overrightarrow{Y}\right)}{P\left(d_k=-1\text{|}\overrightarrow{Y}\right)}<1.& \left[\mathrm{Eqn}.2\right]\end{array}$ From Equation 2, it is noted that a bit is decoded according to the sign of the log-likelihood ratio (LLR). From Bayes theorem, it may be shown:P(d_k=±1|{right arrow over (Y)})=p({right arrow over (Y)}|d_k=±1)P(d_k=±1).  [Eqn. 3]

Combining Equations 2 and 3 and taking the log of both sides yields the log-likelihood ratio (LLR), which is a useful metric in turbo decoding: $\begin{array}{cc}\begin{array}{c}L\left(d_k\right)\equiv \log \left(\frac{P\left(d_k=+1\text{|}\overrightarrow{Y}\right)}{P\left(d_k=-1\text{|}\overrightarrow{Y}\right)}\right)\\ =\log \left(\frac{p\left(\overrightarrow{Y}\text{|}{d}_k=+1\right)}{p\left(\overrightarrow{Y}\text{|}{d}_k=-1\right)}\right)+\log \left(\frac{P\left(d_k=+1\right)}{P\left(d_k=-1\right)}\right)\end{array}& \left[\mathrm{Eqn}.4\right]\end{array}$ It is noted that the last term of the right-hand side of Equation 4 is the extrinsic information and is denoted as L_e (d_k).

MAP Decoding for Binary Turbo Codes

During the iterative process, the extrinsic information, L_e(d_k), is generated by the first decoder (i.e., MAP decoder block 610) and then fed into the second decoder (i.e., MAP decoder block 620). The first term on the right-hand side of Equation 4 has two parts: $\begin{array}{cc}\log \frac{p\left(\overrightarrow{Y}\text{|}{d}_k=+1\right)}{p\left(\overrightarrow{Y}\text{|}{d}_k=-1\right)}=L_c{X}_k+L_a\left(d_k\right)& \left[\mathrm{Eqn}.5\right]\end{array}$

The value L_c, is the channel information and depends solely on the statistic of the channel. For an AWGN channel, $\begin{array}{cc}{L}_c=4\frac{{\mathrm{rE}}_b}{N_0},& \left[\mathrm{Eqn}.6\right]\end{array}$ where r is the code rate. The value, L_a, is the extrinsic information fed back to MAP decoder block 610 by MAP decoder block 620. At the start of the decoding process, L_a is set to zero.

The iterative decoding process goes as follows. First, the a-priori information, L_a(d_k) is calculated from the other decoder by interleaving or deinterleaving its extrinsic information. Next, L_a(d_k) is calculated as shown in Equation 8 below. Finally, the extrinsic information for the other encoder is calculated using:L_e(d_k)=L(d_k)−L_cX_k−L_a(d_k).  [Eqn. 7]

Calculation of LLR—A brief discussion of maximum a-posteriori (MAP) symbol-by-symbol algorithms for convolutional codes is now presented. Three different decoding schemes are discussed: i) Log-MAP; ii) Max-Log-MAP; and iii) Linear Max*-Log-MAP. Because of the large number of multiplications and numerical instabilities, it is preferable to operate in the logarithmic domain in order to solve the numerical problem and reduce processing complexity.

The following notations are used: i) S is the set of all 2^m encoder states; ii) S_k is the encoder state at time k; and iii) S⁺is the set of ordered pairs (s′,s) such that if S_k−1=s′ and the new data input bit is +1, the transition S_k-1=S′→S_k=S occurs. The set S⁻is similarly defined for input bit −1.

The Log-MAP Algorithm—It can be shown that L(d_k) has the following form: $\begin{array}{cc}L\left(d_k\right)=\log \left(\frac{\sum _{S+}\exp \left({\alpha }_{k-1}^s+{\beta }_k^{s^{\prime }}+{\gamma }_k^{1,s^{\prime }\to s}\right)}{\sum _{S-}\exp \left({\alpha }_{k-1}^s+{\beta }_k^{s^{″}}+{\gamma }_k^{-1,s^{″}\to s}\right)}\right).& \left[\mathrm{Eqn}.8\right]\end{array}$ The value α is the forward state metric, the value β is the reverse state metric, and the value γ is the branch metric. The value S+ is the set of ordered pairs (s,s′) corresponding to all state transitions from state s′ at time k-1 to state s at time k due to input bit d_k=+1. The value S− is similarly defined for the case where d_k=−1.

The values α and β are calculated recursively using: $\begin{array}{cc}\begin{array}{c}{\alpha }_k^s=\log \sum _{s^{\prime }}\exp \left({\alpha }_{k-1}^{s^{\prime }}+{\gamma }^{d_k,s\to s^{\prime }}\right),\\ {\beta }_{k-1}^{s^{\prime }}=\log \sum _s\exp \left({\beta }_k^s+{\gamma }^{d_k,s\to s^{\prime }}\right)\end{array}& \left[\mathrm{Eqn}.9\right]\end{array}$

The boundary conditions for α and β are: $\begin{array}{cc}\begin{array}{c}{\alpha }_0^0=0,{\alpha }_0^{s\ne 0}\\ =-\infty ,\\ {\beta }_{N-1}^0=0,{\beta }_{N-1}^{s\ne 0}\\ =-\infty \end{array}& \left[\mathrm{Eqn}.10\right]\end{array}$

The branch metric, γ^d.S→S′ given by: $\begin{array}{cc}{\gamma }^{d_k,s\to s^{\prime }}=\exp \left(\frac{1}{2}\left(d_k{L}_c\left(X_k\right)+\sum _j{L}_c{y}_k^j{Y}_k^j+d_k{L}_e\left(d_k\right)\right)\right)& \left[\mathrm{Eqn}.11\right]\end{array}$ It is noted that the last term in Equation 11 contains the extrinsic information.

The Max-Log-MAP Algorithm—The implementation of the Log-MAP algorithm described above requires significant decoder complexity. The Max-Log-MAP algorithm is a simple approximation of the Log-MAP algorithm. It is noted that the calculation of the forward and reverse path metrics in Equation 9 involves a log-add operation. The max* operator is defined as:max*(x, y)≡log(e^x+e^y).  [Eqn. 12]

When this expression is computed exactly, it equals:max*(x, y)=max(x, y)+log(1−e^|x−y|).  [Eqn. 13]

A zero-order approximation to Equation 13 is obtained by equating:max*(x, y)≈max(x, y).  [Eqn. 14]

Hence, expressions of type $\log \sum _i\exp \left(x_i\right)$ become: $\log \sum _i\exp \left(x_i\right)\approx {\max }_i\left(x_i\right)$

Using this result yields the following approximations for α and β″:α_k^s≈max_s′(α_k−1^s′+γ^dk,s→s′), β_k=1^s≈max_s′(β_k^s′+γ^{dk+1,s→s′})  [Eqn. 16]

The LLR is approximated as:L(d_k)≈max_s,s′dk=1(α_k−1^s′+β_k^s+γ_k^1,s→s′)−max_s,s′dk⁼⁻¹(α_k−1^s′+β_k^s+γ_k^{−1,s→s′})  [Eqn. 17]

The Linear Max*-Log-MAP Algorithm—Since the max* operation is performed twice for each node in the trellis, the numerical errors due to the approximation in Equation 14 may lead to significant performance degradation. The linear Max*-Log-MAP algorithm adds a linear order correction term to Equation 14: $\begin{array}{cc}\max *\left(x,y\right)\approx \max \left(x,y\right)+\{\begin{array}{cc}0& \mathrm{if}x-y>T\\ C\left(x-y-T\right)& \mathrm{if}x-y\le T\end{array}& \left[\mathrm{Eqn}.18\right]\end{array}$ The values of C and T that minimize the mean square error are C=−0.24904 and T=2.5068. These values may be determined by considering a convenient fixed-point implementation.

MAP Decoding for Duo-binary Turbo Codes—Unlike the decoding process for a binary turbo code, in which one binary symbol is represented by one log-likelihood ratio, the decoding process for a duo-binary turbo code calculates three log-likelihood ratios L^(z)(d_k) for each symbol: $\begin{array}{cc}{L}^{\left(z\right)}\left(d_k\right)\equiv \frac{P\left(d_k=z❘\overrightarrow{Y}\right)}{P\left(d_k=00❘\overrightarrow{Y}\right)}=\log \left(\frac{\sum _{s,s^{\prime },z}\exp \left({\alpha }_{k-1}^s+{\beta }_k^{s^{\prime }}+{\gamma }_k^{z,s^{\prime }\to s}\right)}{\sum _{s,s^{\prime }}\exp \left({\alpha }_{k-1}^s+{\beta }_k^{s^{″}}+{\gamma }_k^{00,s^{″}\to s}\right)}\right),& \left[\mathrm{Eqn}.19\right]\end{array}$ where z∈{01,10,11}.

As in the binary case, extrinsic information is generated by one decoder and fed into the other decoder in order to update the log-likelihood ratios. The main difference is that in duo-binary mode, the expression for the extrinsic (λ) information contains no channel information, but is simply a subtraction of the input LLR from the output LLR:L_e^(z)(d_k)=L^(z)(d_k)−L_a^(z)(d_k)  [Eqn. 20]

Calculation of the LLR—The calculation of the LLR follows similar principles to those outlined above for the binary code mode. For duo-binary, the decoding algorithms used are the Log-MAP algorithm and the Max-Log-MAP algorithm.

The Log-MAP Algorithm—The recursive equations for α and β and the boundary conditions are identical to Equations 9 and 10. The branch metric, γ^z,s→s′, is given by:γ^z,s→s′=log(p(Y_k|d_k=z))+log(p(d_k=z))  [Eqn. 21] The last term in Equation 21 contains the extrinsic information, as in the binary code case. The LLR is given by: $\begin{array}{cc}{L}^{\left(z\right)}\left(d_k\right)=\log \left(\frac{\sum _{s,s^{\prime },z}\exp \left({\alpha }_{k-1}^s+{\beta }_k^{s^{\prime }}+{\gamma }_k^{z,s^{\prime }\to s}\right)}{\sum _{s,s^{\prime }}\exp \left({\alpha }_{k-1}^s+{\beta }_k^{s^{″}}+{\gamma }_k^{00,s^{″}\to s}\right)}\right).& \left[\mathrm{Eqn}.22\right]\end{array}$

The Max-Log-MAP Algorithm—As in the binary code case, simple approximations for α and β are given by:α_k^s≈max_s′(α_k−1^s′+γ^dk,s→s′), β_k=1^s≈max_s′(β_k^s′+γ^{dk+1,s→s′})  [Eqn. 23]

The branch metric, γ^z,s→s′, is given by:γ^z,s→s′=log(p(Y_k|d_k=z))+log(p(d_k=z)).  [Eqn. 24]

The last term in Equation 21 contains the extrinsic information, as in the binary case. The LLR is approximated as:L^(z)(d_k)≈max_s,s′z(α_k−1^s′+β_k^s+γ_k^z,s→s′)−max_s,s′(α_k−1^s′+β_k^s+γ_k^00,s→s′)  [Eqn. 25]

From Equations 16 and 23 above, it can be seen that the Max-Log MAP algorithm may calculate the value of alpha (α) for both the binary code mode and duo-binary code mode using Equation 26 below:α_k^s≈max_s′(α_k−1^s′+γ^dk,s→s′).  [Eqn. 26]

Additionally, from Equations 16 and 23 above, it can be seen that the Max-Log MAP algorithm may calculate the value of beta (β) for both the binary code mode and duo-binary code mode using Equation 27 below:β_k=1^s≈max_s′(β_k^s′+γ^{dk+1,s→s′}).  [Eqn. 27]

In Equations 26 and 27, α_k^s and β_k^s−1 are the values for the current states and α_k^s−1 and β_k^s are the values from the previous states.

It is noted that the alpha and beta calculations have the same operations, but different operands. According to the principles of the present disclosure, if the operands are prepared correctly, the alpha and beta calculations may performed by the same arithmetic logic unit (ALU) hardware.

It is further noted that Equations 17 and 25, which the Max-Log MAP algorithm uses to calculate the value of gamma (γ) for both the binary code mode and duo-binary code mode, are very similar to each other. Moreover, it is noted that Equations 17 and 25 use operations that are very similar to the alpha and beta calculations in Equations 26 and 27. Thus, according to the principles of the present disclosure, if the operands are prepared correctly, the lambda calculations may reuse the alpha and beta ALU hardware.

FIGS. 7 and 8 are high-level block diagrams of reconfigurable MAP decoder 700, which may be used in WiBro mode and in WCDMA mode. MAP decoder 700 comprises gamma calculation block 705, arithmetic logic unit (ALU) stage 710, arithmetic logic unit (ALU) stage 715, alpha memory 720, lambda memory 725, interleaver 730, multiplexer 735, multiplexer 740, and optional gamma memory 750. Reconfigurable MAP decoder 700 is a generalized representation of the functions performed by various components in FIG. 4A. For example, ALU stages 710 and 715, multiplexers 735 and 740, and gamma calculation block 705 may be implemented in each of MAP datapaths 432a-d. Similarly, interleaver 730 may be implemented by communication switch 420, lambda memory 725 may be implemented by extrinsic information memories 445a-d 430, alpha memory 720 may be implements by caches 433a-d, and so forth.

The reconfigurable and reprogrammable capabilities of MAP datapaths 432a-d and communication switch (i.e., interleaver) 420 enable reconfigurable MAP decoder 700 to operate in both duo-binary code (i.e., WiBro) systems and in binary code (i.e, WCDMA, HSDPA) systems. In FIG. 7, MAP decoder 700 operates in duo-binary code mode. In FIG. 8, MAP decoder 700 operates in binary code mode.

As will be explained below in greater detail, ALU stage 710 performs the alpha (α) calculations in Equation 26 and the beta (β) calculation in Equation 27 for both binary code mode and duo-binary code mode. No particular architecture is required for ALU stage 710. However, ALU stage 710 comprises an appropriate number of reconfigurable adders and comparators to perform the calculations in Equations 26 and 27.

As will be explained below in greater detail, the calculations of lambda (β) shown in Equations 17 and 25 are divided across ALU stage 710 and ALU stage 715 in both binary code mode and duo-binary code mode. ALU stage 715 also comprises an appropriate number of reconfigurable adders and comparators to perform (along with ALU stage 710) the calculations in Equations 17 and 25.

In the duo-binary code mode in FIG. 7, during a forward recursion, gamma calculation block 705 calculates and stores the branch metrics (or gamma (γ) values) using: i) input symbol information, namely the duo-binary inputs (a, b) and the parity inputs (y, y′, w, w′); and ii) extrinsic (λ) information in lambda memory 525 via interleaver 730. In trellis 499 in FIG. 4B, there are 8 states for each time slot (or input symbol) and 4 branches associated with each state, for a total of 32 branches. In the exemplary embodiment, each soft input data sample comprises s=8 bits. Thus, the gamma output of gamma calculation block 505 is shown as 4×8×s in FIG. 7. Gamma calculation block 505 also receives beta sign select and alpha sign select information. In the exemplary embodiment, there are a total of h=4 sign select bits for each of the 4×8 branches shown in trellis 499. As noted above in FIG. 4A, the gamma value may be stored in gamma memory 750 (e.g., cache 433) in order to reduce power consumption.

In the duo-binary code mode in FIG. 7, during a forward recursion, ALU stage 710 calculates the alpha (α) value for each node in trellis 499. ALU stage receives the previous α value from alpha memory 720 (i.e., cache 433) and, as noted above, receives branch metric information (γ) from gamma calculation block 705. ALU stage 710 receives the alpha trellis information for each node via multiplexer 740. In the exemplary embodiment, each of the eight trellis state in trellis 499 is represented by t=3 bits (i.e., 000-111). Since there are 4×8=32 branches associated with the 8 trellis states, the alpha trellis information is shown as 4×8×t in FIG. 7. ALU stage 710 stores the s=8 bit alpha values for each of the eight trellis nodes in alpha memory 720.

In the duo-binary code mode in FIG. 7, during a backward recursion, ALU stage 710 calculates the beta (β) value for each node in trellis 499. The beta calculation process is very similar to the alpha calculation process. ALU stage 710 receives the previous β value and receives branch metric information (γ) from gamma calculation block 705. ALU stage 710 receives the beta trellis information for each node via multiplexer 740. Like the alpha trellis information, the beta trellis information is shown as 4×8t in FIG. 7.

In the duo-binary code mode in FIG. 7, ALU stage 710 partially calculates the LLR (λ) values in Equation 25 using the α, β, and γ values for each of the 32 branches in trellis 499. ALU stage 715 completes the calculation of the LLR value. In duo-binary mode, the 2×k output of ALU stage 715 may be a hard decision pair of bits (k=1) or a pair of soft values (k=16 bits) that are sent to an external circuit for a decision. As noted above, all lambda values may be normalized by the L00 value, such that ALU stage 715 only needs to store three (3) s=16 bit values for L01, L10 and L11 in lambda memory 725.

The binary code mode in FIG. 8 operates similarly to the duo-binary code mode in FIG. 7. However, whereas duo-binary code operations process two bits (i.e., a and b) from a single time slot, reconfigurable MAP decoder 700 processes two consecutive binary bits from different time slots (k=i and k=i+1) during binary code mode. These two consecutive binary bits are arbitrarily referred to as x_i and x_i+1 in FIG. 8. The corresponding parity bits are y_i and y′_i for the first input bit and y_i+1 and y′_i+1 for the second input bit.

In binary code mode, ALU stage 710 performs the alpha (α) calculations in Equation 26 and the beta (β) calculation in Equation 27. ALU stage 710 partially calculates the LLR (λ) values in Equation 17 using the α, β, and γ values for each of the 32 branches in trellis 499. ALU stage 715 completes the calculation of the LLR value. In binary mode, the 2×k output of ALU stage 715 may be a hard decision pair of bits (k=1) or a pair of soft values (k=16 bits) that are sent to an external circuit for a decision. ALU stage 715 stores two k=16 bit lambda values in lambda memory 725, one for each of the two input samples (i.e, x_i and x_i+1).

Although the present disclosure has been described with an exemplary embodiment, various changes and modifications may be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims.

Claims

1. A reconfigurable maximum a-posteriori probability (MAP) calculation circuit for decoding duo-binary code data and binary code data, the reconfigurable MAP calculation circuit comprising: a gamma calculation block for calculating a branch metric value for each branch of a trellis associated the MAP calculation circuit, wherein the gamma calculation block receives: in duo-binary mode: i) duo-binary inputs (a, b) from a first time interval; ii) parity information generated from the duo-binary inputs (a,b); and iii) extrinsic information associated with previous nodes in the trellis; and in binary mode: i) a first binary input xi from a first time interval and a second binary input xi+1 from a second time interval; ii) first parity information generated from the first binary input xi and second parity information generated from the second binary input xi+1; and iii) extrinsic information associated with previous nodes in the trellis; and a first arithmetic logic unit (ALU) stage for calculating alpha values for each node in the trellis in both duo-binary mode and binary mode, wherein the first ALU stage receives alpha values for previous nodes in the trellis and branch metric data from the gamma calculation block.

2. The reconfigurable MAP calculation circuit as set forth in claim 1, wherein the first ALU stage is further capable of calculating beta values for each node in the trellis in both duo-binary mode and binary mode, wherein the first ALU stage receives beta values for previous nodes in the trellis and branch metric data from the gamma calculation block.

3. The reconfigurable MAP calculation circuit as set forth in claim 2, wherein the first ALU stage calculates the alpha values for each node in the trellis according to the equation:

4. The reconfigurable MAP calculation circuit as set forth in claim 3, wherein the first ALU stage calculates the beta values for each node in the trellis according to the equation:

5. The reconfigurable MAP calculation circuit as set forth in claim 4, further comprising a second ALU stage, wherein the first and second ALU stages are capable of calculating extrinsic information values for the first time interval in duo-binary mode and for the first and second time intervals in binary mode.

6. The reconfigurable MAP calculation circuit as set forth in claim 5, wherein the first and second ALU stages calculate the extrinsic information value for the first time interval in duo-binary mode according to the equation:

7. The reconfigurable MAP calculation circuit as set forth in claim 6, wherein the first and second ALU stages calculate the extrinsic information values for the first and second time intervals in binary mode according to the equation:

8. A reconfigurable turbo decoder comprising: N processing units, each of the N processing units capable of receiving soft input data samples and decoding the received soft input data samples, wherein the N processing units operate independently such that a first one of the N processing units may be selected to decode the received soft input data samples while a second one of the N processing units may be disabled, and wherein each of the N processing units comprises a reconfigurable maximum a-posteriori probability (MAP) calculation circuit for decoding duo-binary code data and binary code data, the reconfigurable MAP calculation circuit comprising: a gamma calculation block for calculating a branch metric value for each branch of a trellis associated the MAP calculation circuit, wherein the gamma calculation block receives: in duo-binary mode: i) duo-binary inputs (a, b) from a first time interval; ii) parity information generated from the duo-binary inputs (a,b); and iii) extrinsic information associated with previous nodes in the trellis; and in binary mode: i) a first binary input xi from a first time interval and a second binary input xi+1 from a second time interval; ii) first parity information generated from the first binary input xi and second parity information generated from the second binary input xi+; and iii) extrinsic information associated with previous nodes in the trellis; and a first arithmetic logic unit (ALU) stage for calculating alpha values for each node in the trellis in both duo-binary mode and binary mode, wherein the first ALU stage receives alpha values for previous nodes in the trellis and branch metric data from the gamma calculation block.

9. The reconfigurable turbo decoder as set forth in claim 8, wherein the first ALU stage is further capable of calculating beta values for each node in the trellis in both duo-binary mode and binary mode, wherein the first ALU stage receives beta values for previous nodes in the trellis and branch metric data from the gamma calculation block.

10. The reconfigurable turbo decoder as set forth in claim 9, wherein the first ALU stage calculates the alpha values for each node in the trellis according to the equation:

11. The reconfigurable turbo decoder as set forth in claim 10, wherein the first ALU stage calculates the beta values for each node in the trellis according to the equation:

12. The reconfigurable turbo decoder as set forth in claim 11, further comprising a second ALU stage, wherein the first and second ALU stages are capable of calculating extrinsic information values for the first time interval in duo-binary mode and for the first and second time intervals in binary mode.

13. The reconfigurable turbo decoder as set forth in claim 12, wherein the first and second ALU stages calculate the extrinsic information value for the first time interval in duo-binary mode according to the equation:

14. The reconfigurable turbo decoder as set forth in claim 13, wherein the first and second ALU stages calculate the extrinsic information values for the first and second time intervals in binary mode according to the equation:

15. A software-defined radio (SDR) system capable of operating under a plurality of wireless communication standards, the SDR system comprising a reconfigurable maximum a-posteriori probability (MAP) calculation circuit for decoding duo-binary code data and binary code data, the reconfigurable MAP calculation circuit comprising: a gamma calculation block for calculating a branch metric value for each branch of a trellis associated the MAP calculation circuit, wherein the gamma calculation block receives: in duo-binary mode: i) duo-binary inputs (a, b) from a first time interval; ii) parity information generated from the duo-binary inputs (a,b); and iii) extrinsic information associated with previous nodes in the trellis; and in binary mode: i) a first binary input xi from a first time interval and a second binary input xi+1 from a second time interval; ii) first parity information generated from the first binary input xi and second parity information generated from the second binary input xi+1; and iii) extrinsic information associated with previous nodes in the trellis; and a first arithmetic logic unit (ALU) stage for calculating alpha values for each node in the trellis in both duo-binary mode and binary mode, wherein the first ALU stage receives alpha values for previous nodes in the trellis and branch metric data from the gamma calculation block.

16. The software-defined radio (SDR) system as set forth in claim 15, wherein the first ALU stage is further capable of calculating beta values for each node in the trellis in both duo-binary mode and binary mode, wherein the first ALU stage receives beta values for previous nodes in the trellis and branch metric data from the gamma calculation block.

17. The software-defined radio (SDR) system as set forth in claim 16, wherein the first ALU stage calculates the alpha values for each node in the trellis according to the equation:

18. The software-defined radio (SDR) system as set forth in claim 17, wherein the first ALU stage calculates the beta values for each node in the trellis according to the equation:

19. The software-defined radio (SDR) system as set forth in claim 18, further comprising a second ALU stage, wherein the first and second ALU stages are capable of calculating extrinsic information values for the first time interval in duo-binary mode and for the first and second time intervals in binary mode.

20. The software-defined radio (SDR) system as set forth in claim 19, wherein the first and second ALU stages calculate the extrinsic information value for the first time interval in duo-binary mode according to the equation:

21. The software-defined radio (SDR) system as set forth in claim 20, wherein the first and second ALU stages calculate the extrinsic information values for the first and second time intervals in binary mode according to the equation: