The present invention relates to the manufacture of integrated circuits. More particularly, the present invention provides a technique for forming a gettering layer in a silicon-on-insulator wafer made using a controlled cleaving process, for example.
Integrated circuits are fabricated on chips of semiconductor material. These integrated circuits often contain thousands, or even millions, of transistors and other devices. In particular, it is desirable to put as many transistors as possible within a given area of semiconductor because more transistors typically provide greater functionality, and a smaller chip means more chips per wafer and lower costs.
Some integrated circuits are fabricated on a slice or wafer, of single-crystal (monocrystalline) silicon, commonly termed a “bulk” silicon wafer. Devices on such “bulk” silicon wafer typically are isolated from each other. A variety of techniques have been proposed or used to isolate these devices from each other on the bulk silicon wafer, such as a local oxidation of silicon (“LOCOS”) process and others. These techniques, however, are not free from limitations. For example, conventional isolation techniques consume a considerable amount of valuable wafer surface area on the chip, and often generate a non-planar surface as an artifact of the isolation process. Either or both of these considerations generally limit the degree of integration achievable in a given chip.
An approach to achieving very-large scale integration (VLSI) or ultra-large scale integration (ULSI) is by using a semiconductor-on-insulator (SOI) wafer. An SOI wafer typically has a layer of silicon on top of a layer of an insulator material. A variety of techniques have been proposed or used for fabricating the SOI wafer. These techniques include, among others, growing a thin layer of silicon on a sapphire substrate, bonding a layer of silicon to an insulating substrate, and forming an insulating layer beneath a silicon layer in a bulk silicon wafer. In an SOI integrated circuit, essentially complete device isolation is often achieved using conventional device processing methods by surrounding each device, including the bottom of the device, with an insulator. An advantage SOI wafers have over bulk silicon wafers is that the area required for isolation between devices on an SOI wafer is less than the area typically required for isolation on a bulk silicon wafer.
SOI offers other advantages over bulk silicon technologies as well. For example, SOI offers a simpler fabrication sequence compared to a bulk silicon wafer. Devices fabricated on an SOI wafer may also have better radiation resistance, less photo-induced current, and less cross-talk than devices fabricated on bulk silicon wafers. However, many problems that have already been solved regarding fabricating devices on bulk silicon wafers remain to be solved for fabricating devices on SOI wafers.
Numerous limitations, however, still exist with the fabrication of SOI wafers. For example, devices within integrated circuits in SOI wafers are very sensitive to the presence of even minute concentrations of some impurities. For example, metals, such as copper, nickel, silver, gold, or iron, within the active region of a device typically degrade several device characteristics, including leakage current and breakdown voltage. These and other metals rapidly diffuse through silicon at temperatures typical of semiconductor device fabrication processes. These impurities often become trapped in the active region of the SOI wafer. That is, the SOI wafer includes a dielectric layer or insulating layer underlying the active region that tends to keep impurities in the active layer, rather than diffusing down into the bulk silicon. Accordingly, SOI wafers are prone to device and reliability problems caused by the presence of impurities that cannot diffuse out of the active region.
From the above, it is seen that a technique for removing impurities from active regions of an integrated circuit made on an SOI wafer is highly desirable.
According to the present invention, a technique including a method and device for removing impurities from an SOI wafer made using a controlled cleaving process is provided. In an exemplary embodiment, the present invention provides an SOI wafer with a gettering layer for removing impurities from an active region. This gettering layer removes impurities from the device, thereby preventing a possibility of quality and reliability problems, e.g., lowered breakdown voltage, increased leakage current, and the like. Additionally, the gettering layer provides for “lifetime” engineering of the device made on the SOI wafer.
In a specific embodiment, the present invention provides an SOI wafer made by way of a “cleaving” process with an implanted gettering layer. The process includes a step of providing an SOI wafer, where the thin layer of material (e.g., silicon) was bonded onto an insulating layer. Gas-forming particles, such as hydrogen or helium ions, are implanted or introduced into the thin layer of material or other region of the SOI wafer. The SOI wafer is thermally processed so that the implanted particles create, for example, microbubbles or implanted precipitates in the wafer. These microbubbles act as gettering sites for impurities in the thin layer of material. Alternatively, the particles act as gettering sites for the impurities. The thin layer of material has been separated from, for example, a bulk donor silicon wafer by a controlled cleaving process, such as the one described in U.S. Provisional Application Ser. No. 60/046,276 in the name of Henley et al. (“Henley”), which is hereby incorporated by reference for all purposes.
In an alternative embodiment, the present invention provides an SOI wafer made by way of a cleaving process with a deposited gettering layer. The gettering layer is, for example, a layer of polysilicon, which can be patterned, formed on a bulk monocrystalline silicon donor or receptor wafer. The thin layer of material, including the gettering layer, has been separated from, for example, a bulk donor silicon wafer by a controlled cleaving process. A gettering layer, such as a layer of polysilicon, on the thin layer, such as a layer of monocrystalline silicon, can provide effective gettering after a different time-temperature product, i.e. thermal budget, than microbubbles. Thus, a gettering layer on the thin layer can be used in addition to or alternatively to microbubble or particle gettering sites.
Numerous benefits are achieved by way of the present invention over pre-existing techniques. These benefits include, among others, gettering of impurities from active regions of an integrated circuit device made on an SOI wafer. Additionally, the present invention occurs by way of improved processing techniques using PIII, for example. PIII is relatively cost effective, easy to use and in some instances produces less impurity metal contamination than other ion implantation techniques. Furthernore, the present technique provides “lifetime” engineering of the device, which is likely to have improved reliability from the present gettering layer(s). These and other benefits are described throughout the specification and more particularly below.
These and other embodiments of the present invention, as well as its advantages and features are described in more detail in conjunction with the text below and attached figures.
The present invention provides an SOI wafer with a gettering layer for removing impurities from an active region of an integrated circuit to be formed on the wafer. In a specific embodiment, a gettering layer is formed in an SOI wafer made using a controlled cleaving process. The gettering layer is generally beneath an active region of the devices that will be formed on the SOI wafer. The SOI wafer is made using a controlled cleaving process, which is described in Henley, noted above.
1. Silicon on Insulator Substrate
2. Controlled Cleaving Process
A process for fabricating a silicon-on-insulator substrate having a gettering layer using the controlled cleaving process may be briefly outlined as follows:
Selected energetic particles 203 implant through the top surface of the silicon wafer to a selected depth, which defines the thickness of the material region, termed the thin film of material. As shown, the particles have a desired concentration 205 at the selected depth (z0). A variety of techniques can be used to implant the energetic particles into the silicon wafer. These techniques include ion implantation using, for example, beam line ion implantation equipment manufactured from companies such as Applied Materials, Eaton Corporation, Varian, and others. Alternatively, implantation occurs using a plasma immersion ion implantation (“PIII”) technique. Of course, techniques used depend upon the application, such as an ion shower technique.
Depending upon the application, smaller mass particles are generally selected to reduce a possibility of damage to the material region. That is, smaller mass particles easily travel through the substrate material to the selected depth without substantially damaging the material region that the particles traversed through. For example, the smaller mass particles (or energetic particles) can be almost any charged (e.g., positive or negative) and/or neutral atoms or molecules, or electrons, or the like. In a specific embodiment, the particles can be neutral and/or charged particles including ions such as H+ ions, rare gas ions such as helium and its isotopes, and neon, and deuterium. The particles can also be derived from compounds such as gases, e.g., hydrogen gas, water vapor, methane, hydrides, and hydrogen compounds, and other light atomic mass particles. Alternatively, the particles can be any combination of the above particles, and/or ions and/or molecular species and/or atomic species.
A gettering layer can be defined in the donor substrate using a variety of techniques.
In most of the embodiments, the distribution of these gettering sites depends upon the energies used to implant the gas-forming particles, among other factors. In this instance, the gettering layer is made up of several microbubbles distributed over a range of depth from the top surface of the wafer. The microbubbles formed after thermally treating the implanted gas-forming particles. The choice of ion dosage and energy to form the gettering layer depends upon many factors, including the depth of the insulator layer, the type of semiconductor material the gettering layer is to be formed in, the bubble-forming species, and the intended device type and active region, among other factors. As an example, 1×1017 cm−2 helium ions implanted into a {100} silicon wafer at 30 keV and annealed for one-half hour at 700° C. resulted in a layer of microbubbles in the silicon wafer about 0.3 μm below the top surface of the wafer. The bubbles can have an average diameter of about 8 nm. Annealing for longer periods of time or at a higher temperature resulted in larger bubbles being formed, resulting in a reduction of total microbubble surface area. High-temperature annealing also generally reduces the dislocations, stacking faults, and other crystal imperfections associated with microbubble gettering. The implantation of gas-forming particles, as well as the implantation of insulator-forming particles, may be performed by a variety of techniques, including ion beam implantation and plasma immersion ion implantation (PIII).
In an alternative embodiment, a gettering layer can be defined using a deposited layer 405 in the substrate 400, as shown by FIG. 4. The deposited layer can be a variety of materials including polysilicon or heavily doped N-type polysilicon, which is often doped using phosphorous or the like. The polycrystalline silicon layer may be formed by a variety of conventional techniques, and will eventually become a gettering layer in an SOI wafer. It is understood that a layer of amorphous silicon could be formed instead of the polysilicon layer, but polysilicon layers typically have small grains, which are advantageous for gettering impurities. Heavily doped polysilicon can also be used, for example. In some embodiments, the polysilicon is doped using phosphorous or the like. The polysilicon can be doped via diffusion or implantation or in-situ doped, depending upon the application.
Grain boundaries and high degree of lattice disorder in the polysilicon act as sinks for mobile impurities. The polysilicon layer provides gettering sites that differ from the sites provided by microbubbles. For example, the grain boundaries and lattice disorder associated with polysilicon do not anneal out at the same time-temperature product as some of the gettering sites provided by microbubbles. The polysilicon layer may further include impurities, such as oxygen or other precipitate-forming impurities, or lattice-strain-inducing impurities, such as phosphorous, to further improve the effectiveness of the gettering layer.
In yet an alternative specific embodiment, the present invention provides a gettering layer 501, which is defined on the top surface of the substrate 500, as illustrated by FIG. 5. As shown, particles 503 are introduced into a region directly in the insulating layer to define the gettering layer 501. These particles can include a variety of materials, which form either gas bubbles or implanted precipitates such as those described above, but can be others.
In a modification to any of the above embodiments, the gettering layer including those implanted or deposited can be patterned. For example, the pattern can be formed by a “shadow” mask, or masking and photolithography steps. Additionally, a variety of patterns can be used depending upon the applications. For instance, the patterns can be in the form of a plurality of strips, numerous concentric circles, a checkerboard, and others. Alternatively, the implanted region can be specifically placed in to be non-active regions of the device. These non-active regions include, among others, field isolation oxide regions, peripheral regions of the device, and “streets.” Of course, the type of pattern used depends highly upon the application.
The process uses a step of joining the implanted silicon wafer (e.g., 300, 400, or 500) to a workpiece or receptor wafer 600, as illustrated in FIG. 6. The workpiece may also be a variety of other types of substrates such as those made of a dielectric material (e.g., glass, silicon nitride, silicon dioxide), a conductive material (polysilicon, group III/V materials, metal), and plastics (e.g., polyimide-based materials). In the present example, however, the workpiece is a silicon wafer.
In a specific embodiment, a gettering layer can be defined on the receptor or target wafer 600. For example, the gettering layer can be made of particles, which are implanted into an insulating layer 601 as shown by reference letter B. Alternatively, the gettering layer can be made of particles, which are implanted into a region underlying the insulating layer 601 as shown by reference letter A. Furthermore, deposition techniques such as chemical vapor deposition or physical vapor deposition is used to form a gettering layer in either region A or B. This gettering layer can be made of a variety of materials including polysilicon, amorphous silicon, heavily doped polysilicon, and others. The heavily doped polysilicon includes, among other materials, phosphorous doped polysilicon, which is implanted, diffused, or in-situ doped. The gettering layer in the receptor wafer can be combined with any of the other gettering layers defined throughout the present specification, as well as others.
In a modification to any of the above embodiments using the receptor substrate, the gettering layer including those implanted or deposited can be patterned. For example, the pattern can be formed by a “shadow” mask or masking and photolithography steps. Additionally, a variety of patterns can be used depending upon the applications. For instance, the patterns can be in the form of a plurality of strips, numerous concentric circles, a checkerboard, and others. Alternatively, the implanted region can be specifically placed in to be non-active regions of the device. These non-active regions include, among others, field isolation oxide regions, peripheral regions of the device, and “streets.” Of course, the type of pattern used depends highly upon the application.
In a specific embodiment, the silicon wafers are joined or fused together using a low temperature thermal step. The low temperature thermal process generally ensures that the implanted particles do not place excessive stress on the material region, which can produce an uncontrolled cleave action. In one aspect, the low temperature bonding process occurs by a self-bonding process. In particular, one wafer is stripped to remove oxidation therefrom (or one wafer is not oxidized). A cleaning solution treats the surface of the wafer to form O—H bonds on the wafer surface. An example of a solution used to clean the wafer is a mixture of H2O2—H2SO4. A dryer dries the wafer surfaces to remove any residual liquids or particles from the wafer surfaces. Self-bonding occurs by placing a face of the cleaned wafer against the face of an oxidized wafer.
Alternatively, a self-bonding process occurs by activating one of the wafer surfaces to be bonded by plasma cleaning. In particular, plasma cleaning activates the wafer surface using a plasma derived from gases such as argon, ammonia, neon, water vapor, and oxygen. The activated wafer surface is placed against a face of the other wafer, which has a coat of oxidation thereon. The wafers are in a sandwiched structure having exposed wafer faces. A selected amount of pressure is placed on each exposed face of the wafers to self-bond one wafer to the other.
Alternatively, an adhesive disposed on the wafer surfaces is used to bond one wafer onto the other. The adhesive includes an epoxy, polyimide-type materials, and the like. Spin-on-glass layers can be used to bond one wafer surface onto the face of another. These spin-on-glass (“SOG”) materials include, among others, siloxanes or silicates, which are often mixed with alcohol-based solvents or the like. SOG can be a desirable material because of the low temperatures (e.g., 150 to 250° C.) often needed to cure the SOG after it is applied to surfaces of the wafers.
Alternatively, a variety of other low temperature techniques can be used to join the donor wafer to the receptor wafer. For instance, an electrostatic bonding technique can be used to join the two wafers together. In particular, one or both wafer surface(s) is charged to attract to the other wafer surface. Additionally, the donor wafer can be fused to the receptor wafer using a variety of commonly known techniques. Of course, the technique used depends upon the application.
After bonding the wafers into a sandwiched structure 700, as shown in
The controlled cleaving action is also illustrated by way of FIG. 7. For instance, a process for initiating the controlled cleaving action uses a step of providing energy 701, 703 to a selected region of the substrate to initiate a controlled cleaving action at the selected depth (z0) in the substrate, whereupon the cleaving action is made using a propagating cleave front to free a portion of the substrate material to be removed from the substrate. In a specific embodiment, the method uses a single impulse to begin the cleaving action. Alternatively, the method uses an initiation impulse, which is followed by another impulse or successive impulses to selected regions of the substrate. Alternatively, the method provides an impulse to initiate a cleaving action which is sustained by a scanned energy along the substrate. Alternatively, energy can be scanned across selected regions of the substrate to initiate and/or sustain the controlled cleaving action.
Optionally, an energy or stress of the substrate material is increased toward an energy level necessary to initiate the cleaving action, but not enough to initiate the cleaving action before directing an impulse or multiple successive impulses to the substrate according to the present invention. The global energy state of the substrate can be raised or lowered using a variety of sources such as chemical, mechanical, thermal (sink or source), or electrical, alone or in combination. The chemical source can include particles, fluids, gases, or liquids. These sources can also include chemical reaction to increase stress in the material region. The chemical source is introduced as flood, time-varying, spatially varying, or continuous. In other embodiments, a mechanical source is derived from rotational, translational, compressional, expansional, or ultrasonic energies. The mechanical source can be introduced as flood, time-varying, spatially varying, or continuous. In further embodiments, the electrical source is selected from an applied voltage or an applied electromagnetic field, which is introduced as flood, time-varying, spatially varying, or continuous. In still further embodiments, the thermal source or sink is selected from radiation, convection, or conduction. This thermal source can be selected from, among others, a photon beam, a fluid jet, a liquid jet, a gas jet, an electro/magnetic field, a gas jet, an electron beam, a thermoelectric heating, and a furnace. The thermal sink can be selected from a fluid jet, a liquid jet, a gas jet, a cryogenic fluid, a super-cooled liquid, a thermoelectric cooling means, an electro/magnetic field, and others. Similar to the previous embodiments, the thermal source is applied as flood, time-varying, spatially varying, or continuous. Still further, any of the above embodiments can be combined or even separated, depending upon the application. Of course, the type of source used depends upon the application. As noted, the global source increases a level of energy or stress in the material region without initiating a cleaving action in the material region before providing energy to initiate the controlled cleaving action.
In a preferred embodiment, the method maintains a temperature which is below a temperature of introducing the particles into the substrate. In some embodiments, the substrate temperature is maintained between −200 and 450° C. during the step of introducing energy to initiate propagation of the cleaving action. Substrate temperature can also be maintained at a temperature below 400° C. or below 350° C. In preferred embodiments, the method uses a thermal sink to initiate and maintain the cleaving action, which occurs at conditions significantly below room temperature. Details of the controlled cleaving process is described in Henley, as previously noted.
A final bonding step occurs between the receptor wafer and thin film of material region according to some embodiments, as illustrated by FIG. 8. In one embodiment, one silicon wafer has an overlying layer of silicon dioxide, which is thermally grown overlying the face before cleaning the thin film of material. The silicon dioxide can also be formed using a variety of other techniques, e.g., chemical vapor deposition. The silicon dioxide between the wafer surfaces fuses together thermally in this process.
In some embodiments, the oxidized silicon surface from either the receptor wafer or the thin film of material region (from the donor wafer) are further pressed together and are subjected to an oxidizing ambient 801, as shown in
Alternatively, the two silicon surfaces are further pressed together and subjected to an applied voltage between the two wafers. The applied voltage raises temperature of the wafers to induce a bonding between the wafers. This technique limits the amount of crystal defects introduced into the silicon wafers during the bonding process, since substantially no mechanical force is needed to initiate the bonding action between the wafers. Of course, the technique used depends upon the application.
After bonding the wafers, silicon-on-insulator has a receptor substrate 807 with an overlying film of silicon material 809 and a sandwiched oxide layer 705 between the receptor substrate and the silicon film, as also illustrated in
Alternatively, chemical mechanical polishing or planarization (“CMP”) techniques finish the detached surface of the film, as illustrated by FIG. 9. In CMP, a slurry mixture is applied directly to a polishing surface 901 which is attached to a rotating platen 903. This slurry mixture can be transferred to the polishing surface by way of an orifice, which is coupled to a slurry source. The slurry is often a solution containing an abrasive and an oxidizer, e.g., H2O2, KIO3, ferric nitrate. The abrasive is often a borosilicate glass, titanium dioxide, titanium nitride, aluminum oxide, aluminum trioxide, iron nitrate, cerium oxide, silicon dioxide (colloidal silica), silicon nitride, silicon carbide, graphite, diamond, and any mixtures thereof. This abrasive is mixed in a solution of deionized water and oxidizer or the like. Preferably, the solution is acidic.
This acid solution generally interacts with the silicon material from the wafer during the polishing process. The polishing process preferably uses a poly-urethane polishing pad. An example of this polishing pad is one made by Rodel and sold under the tradename of IC-1000. The polishing pad is rotated at a selected speed. A carrier head which picks up the receptor wafer having the film applies a selected amount of pressure on the backside of the receptor wafer such that a selected force is applied to the film. The polishing process removes about a selected amount of film material, which provides a relatively smooth film surface 1001 for subsequent processing, as illustrated by FIG. 10.
In certain embodiments, a thin film of oxide overlies the film of material overlying the receptor wafer. The oxide layer forms during the thermal annealing step, which is described above for permanently bonding the film of material to the receptor wafer. In these embodiments, the finishing process is selectively adjusted to first remove oxide and the film is subsequently polished to complete the process. Of course, the sequence of steps depends upon the particular application.
In a further alternative embodiment, the gettering layer 1103 can be formed by way of implanting gas forming particles or precipitate forming particles 1101 after forming the SOI wafer using the controlled cleaving process, as illustrated by FIG. 11.
In most of the embodiments, the distribution of these gettering sites depends upon the energies used to implant the gas-forming particles, among other factors. In this instance, the gettering layer is made up of several microbubbles distributed over a range of depth from the top surface of the wafer. The microbubbles formed after thermally treating the implanted gas-forming particles. The choice of ion dosage and energy to form the gettering layer depends upon many factors, including the depth of the insulator layer, the type of semiconductor material the gettering layer is to be formed in, the bubble-forming species, and the intended device type and active region, among other factors. As an example, 1×1017 cm−2 helium ions implanted into a {100} silicon wafer at 30 keV and annealed for one-half hour at 700° C. resulted in a layer of microbubbles in the silicon wafer about 0.3 μm below the top surface of the wafer. The bubbles can have an average diameter of about 8 nm. Annealing for longer periods of time or at a higher temperature resulted in larger bubbles being formed, resulting in a reduction of total microbubble surface area. High-temperature annealing also generally reduces the dislocations, stacking faults, and other crystal imperfections associated with microbubble gettering. The implantation of gas-forming particles, as well as the implantation of insulator-forming particles, may be performed by a variety of techniques, including ion beam implantation and plasma immersion ion implantation (PIII). Although the embodiment of
In a specific embodiment, the silicon-on-insulator substrate undergoes a series of process steps for formation of integrated circuits thereon. These processing steps are described in S. Wolf, Silicon Processing for the VLSI Era (Volume 2), Lattice Press (1990), which is hereby incorporated by reference for all purposes. A portion of a completed wafer 1200 including integrated circuit devices is illustrated by
While the above is a complete description of specific embodiments of the present invention, various modifications, variations, and alternatives may be employed. For example, a silicon alloy may be substituted for the polysilicon gettering layer. Furthermore, the donor wafer does not have to be silicon, but could be another semiconductor material, such as germanium, silicon carbide, silicon-germanium alloy, or a heterostructure, among others. In such an instance, the gettering layer material would be chosen such that it is appropriate according to the principles discussed above. That is, the gettering layer would be chosen so that it provided an impurity sink in relation to the material used in the active region of devices. Other variations will be apparent to persons of skill in the art. These equivalents and alternatives are intended to be included within the scope of the present invention.
Therefore, the scope of this invention should not be limited to the embodiments described, and should instead be defined by the following claims.
This application claims priority from the provisional patent application entitled GETTERING TECHNIQUE FOR WAFERS MADE USING A CONTROLLED CLEAVING PROCESS, filed Jul. 18, 1997 and assigned Application No. 60/059,980.
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Number | Date | Country | |
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20040097055 A1 | May 2004 | US |
Number | Date | Country | |
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60059980 | Jul 1997 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 09631891 | Aug 2000 | US |
Child | 10402356 | US | |
Parent | 09025958 | Feb 1998 | US |
Child | 09631891 | US |