Glass based empty substrate integrated waveguide devices

Abstract

The present invention includes a method of creating high Q empty substrate integrated waveguide devices and/or system with low loss, mechanically and thermally stabilized in photodefinable glass ceramic substrate. The photodefinable glass ceramic process enables high performance, high quality, and/or low-cost structures. Compact low loss RF empty substrate integrated waveguide devices are a cornerstone technological requirement for RF systems, in particular, for portable systems.

Description

TECHNICAL FIELD OF THE INVENTION

The present invention relates in general to the field of glass based empty substrate integrated waveguide devices. More particularly, the present invention relates to the reduction of parasitic capacitance from fringe capacitance in an RF capacitive resonate filter on the same substrate or in a package.

STATEMENT OF FEDERALLY FUNDED RESEARCH

None.

BACKGROUND OF THE INVENTION

Without limiting the scope of the invention, its background is described in connection with reduction of parasitic capacitance from fringe capacitance.

The tradeoffs with any transmission media line starts with its attenuation characteristics. Traditional Empty waveguide (EW) devices have been used in many applications, however, these have a significant number of advantages and disadvantages relative to other traditional waveguide devices. FIG. 1 shows an image of a traditional waveguide device 10 of the prior art.

Several advancements have been made including empty substrate integrate waveguide (ESIW) devices, such as those developed by Belenguer, et al. A. Belenguer, H. Esteban, and V. E. Boria, “Novel empty substrate integrated waveguide for high-performance microwave integrated circuits,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 4, pp. 832-839, 2014, and B. A. Belenguer, J. L. Cano, H. Esteban, E. Artal, and V. E. Boria, “Empty substrate integrated waveguide technology for E plane high-frequency and high-performance circuits,” Radio Sci., vol. 52, no. 1, pp. 49-69, 2017. The initial efforts show the ESIW using the substrate to support the bottom of the ESIW. Other versions used a metal plate on the printed circuit board (PCB) as the bottom of the ESIW, which eliminates substrate losses from sitting on top of, or as a part of, the PCB substrate. The metal plate on PCB design eliminated or substantially reduced the dielectric loss associated with the substrate, but it introduced additional losses associated with surface roughness and the mechanical distortion of the PCB substrate. Generally, the surface roughness losses are less than the dielectric losses, however, the PCB mechanical from the distortion can be large enough to make the ESIW device completely non-functional. FIG. 2 shows the dimension definition of rectangular substrate integrated 20 of the prior art.

The advantages of traditional ESIW devices include: (1) less metal it used that carries the signal, which is far greater than it would be in microstrip or stripline device; (2) they can be manufactured at a low cost and easy to manufacture using a standard printed circuit board (PCB) substrate; (3) lower transmission losses and higher Q resonators and filters than other planar transmission lines; (4) lower cut-off frequency than traditional waveguide; and (5) higher peak power handling capability. However, these advantages of traditional ESIW devices bring with them certain significant disadvantages, including: (1) leakage losses, which are substantial, based how tight the vias are spaced; (2) dielectric losses of the filled or partially filled guided structure that contributes to the overall dielectric losses (loss tangent) of the substrate integrate waveguide (SIW) device, as a result, dielectric filled SIW are not considered applicable for millimeter-wave frequencies; (3) losses due to conductivity of a free-standing metal substrate are close to zero if a smooth substrate is selected that does not distort over time; (4) ESIWs have a larger footprint compared to the dielectric filled SIWs; and (5) the roughness of the outer face of the copper foil top and bottom of the ESIW device. The roughness of the copper foil/plate (0.3 μm on Rogers 5880 substrate) and on the inner face (0.4 μm), which roughness contributes to the RF losses.

ESIW can be thought of as a dielectric filled waveguide (DFW) where the dielectric constant is 1 and the loss tangent is zero. For TE₁₀ mode, the dimension “b” is not important, as it does not affect the cut off frequency of the waveguide. The substrate can be at any thickness; it only affects the dielectric loss (thicker=lower loss). For a rectangular empty substrate integrated waveguide, cut off frequency of arbitrary mode is found by the following formula:

Empty Substrate Integrated Waveguide are guided by the following formula:

$f_c=\frac{c}{2\pi }\sqrt{{\left(\frac{m\pi }{a}\right)}^2+{\left(\frac{n\pi }{b}\right)}^2},$

where: c is the speed of light, and m, n are mode numbers, a, b: are the vertical and horizontal dimensions of the waveguide.

Published literature on ESIW design requires the following two conditions to be met.

${\lambda }_{\mathrm{guide}}=\frac{{\lambda }_{\mathrm{Free}\mathrm{space}}}{\sqrt{1-{\left(\frac{{\lambda }_{\mathrm{Free}\mathrm{space}}}{{\lambda }_{\mathrm{cutoff}}}\right)}^2}}{\lambda }_{\mathrm{guide}}=\frac{c}{f}\times \frac{1}{\sqrt{1-{\left(\frac{c}{2a·f}\right)}^2}}$

A dielectricless SIW (DSIW) or Empty SIW was first presented in 2016. In this design of the prior art, a thick substrate was milled, metallized, and then covered with a top metallic cover stuck with a prepreg layer (preimpregnated composite fibers, where a thermoset polymer matrix material, such as epoxy, is present), so that it is almost dielectric-free.

The earliest ESIW was proposed by Belenguer in which they removed part of the dielectric body in the substrate to reduce the power dissipated in the dielectric. The emptied substrate had to be closed with top and bottom conducting layers. These layers could be simple, low-cost FR4 substrates, and the authors proposed to affix the layers to the central substrate using a prepreg PCB. The via holes forming the walls of the waveguide could be of any of the plated-through, buried, or blind types. The vias and lateral walls would be metallized using a standard procedure of PCB. As a result, the lateral walls of the waveguide are formed. The waveguide is closed by attaching two metallic covers to the main PCB substrate. One of the covers acts as the upper waveguide wall while the other becomes the lower face of the waveguide 30 (see Prior Art FIG. 3). The electrical connection among these different layers must be of very high quality, otherwise, the device will not function adequately. This high-quality interlayer connection is achieved by means of soldering. A tin soldering paste was used to solder the different layers. This soldering paste is distributed on the top and bottom of the main layer. The structure is assembled, and, finally, the solder paste is dried in a reflow oven.

However, despite these improvements, a need remains for a low loss RF ESIW structure that can be manufactured using commonly available equipment and methods, without the significant disadvantages of current ESIWs.

SUMMARY OF THE INVENTION

In one embodiment, the present invention includes a method of making an empty substrate integrated waveguide (ESIW) device including antenna and RF signal launch elements comprising, consisting essentially of, or consisting of, the steps of: forming an ESIW pattern, an ESIW supports RF signal launch, a perimeter ground patterns and one or more edges of a waveguide on a wafer comprising lithium ions; annealing the exposed pattern in the presence of silver ions at a temperature that enables silver ions to coalesce into silver nanoparticles, and increasing the temperature to between 520° C.-620° C. to allow lithium oxide to form around the silver nanoparticles; coating a topside of the wafer with a photoresist; exposing and developing a pattern to protect the waveguide pattern while leaving the ground pattern exposed; spinning on a blanket photoresist on a backside of the wafer and etching exposed ground ceramic portions in an HF bath; removing the photoresist leaving one or more ground pattern openings and a ceramic waveguide; electroplating copper on the open ground pattern until all ground openings are filled; coating a backside of the wafer with photoresist; exposing and developing a rectangular element with one or more small etch release features; depositing 200 Å to 2,000 Å of titanium metal to form a first titanium layer, followed by a 1 μm deposition of copper onto the backside of the wafer; removing the photoresist leaving a rectangular copper element to form a bottom of the ESIW structure that is electrically connected to the ground pattern copper and waveguide launching element; exposing and developing a rectangular element in photoresist that is oversized over the ceramic ESIW pattern with the one or more etch release features; electroplating copper on the exposed copper areas with between 5-50 μm of copper to improve the rigidity of the ESIW structure; depositing 200 Å to 2,000 Å of titanium metal to form a second titanium layer followed by a 0.5 um to 1 μm deposition of copper onto the topside of the wafer; coating the top side of the wafer with a photoresist; exposing and developing a top side ESIW pattern; using a standard photoresist stripper, copper etchant and titanium etchant to remove the photoresist and to etch any exposed deposition metal, leaving the electroplated copper ESIW patterns; placing wafer is a 0.5% to 50% HF ultrasonic bath; and washing the wafer to remove the HF to obtain the empty substrate integrated waveguide device including antenna and RF signal launch elements. In one aspect, the ESIW has a Q greater than 40. In another aspect, the ESIW has a lower cut-off frequency than a printed circuit board waveguide device at the same frequency. In another aspect, the ESIW has a higher peak power handling capability than a printed circuit board waveguide device at the same frequency. In another aspect, the first, the second, or both first and second titanium layers have a thickness of 300 Å.

In another embodiment, the present invention includes a method of creating a empty substrate integrated waveguide system including at least one or more of a phase matching, time delay, crossover or filter elements, connected to an antenna and RF signal launch element, comprising, consisting essentially of, or consisting of: exposing to an ESIW pattern, an ESIW support, RF signal launch, perimeter ground patterns, and the edges of a waveguide; annealing the exposed pattern temperature enabling the coalesces silver ions into silver nanoparticles; annealing the exposed pattern temperature range heated between 520° C.-620° C. for allowing the lithium oxide to form around the silver nanoparticles; coating a topside of the wafer with a photoresist and exposing and developing a pattern to protect the waveguide pattern while leaving the ground pattern exposed; spinning on blanket photoresist on to the backside of the wafer and HF bath to etch the exposed ground ceramic portions; removing the photoresist to leave ground pattern openings and ceramic waveguide; electroplating copper on the open ground pattern until all ground openings are filled; coating a backside of the wafer with photoresist; and exposing and developing a rectangular element with one or more small etch release features; depositing 200 Å to 2,000 Å of titanium metal to form a first titanium layer followed by a 1 μm deposition of copper onto the backside of the wafer; removing the photoresist to leave a rectangular copper element for the bottom of the ESIW structure that is electrically connected to the ground pattern copper and waveguide launching element; exposing and developing a rectangular element in photoresist that is oversized of the ceramic ESIW pattern with one or more etch release features; electroplating copper on the exposed copper areas with between 5-50 um of copper in order to improve the rigidity of the ESIW structure; depositing 200 Å to 2,000 Å of titanium metal to form a second titanium layer followed by a 0.5 um to 1 μm deposition of copper onto the topside of the wafer; coating the top side of the wafer with photoresist; exposing and developing a top side ESIW pattern and patterns for the RF signal launch elements and the antenna elements, and at least one the Phase matching elements, the time delay elements, or the filter elements and; using a standard photoresist stripper, copper etchant and titanium etchant to remove the photoresist and to etch any exposed deposition metal, leaving an electroplated copper ESIW patterns; placing the wafer into a 0.5% to 50% HF in an ultrasonic bath; and washing the wafer to remove the HF. In another aspect, the ESIW has a Q greater than 20, 30, 35, 36, 37, 38, 39, or 40. In another aspect, the ESIW has a Lower cut-off frequency than a printed circuit board waveguide device at the same frequency. In another aspect, the ESIW has higher peak power handling capability than an ESIW. In another aspect, the first, the second, or both first and second titanium layers have a thickness of 300 Å.

In one embodiment, the present invention includes a high Q empty substrate integrated waveguide devices and/or system with low loss, mechanically and thermally stabilized in a photodefinable glass ceramic substrate. In one aspect, the ESIW has a Q greater than 20, 30, 35, 36, 37, 38, 39, or 40. In another aspect, the ESIW has a lower cut-off frequency than a printed circuit board waveguide device at the same frequency. In another aspect, the ESIW has a higher peak power handling capability than a printed circuit ESIW.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the features and advantages of the present invention, reference is now made to the detailed description of the invention along with the accompanying figures and in which:

FIG. 1 shows a traditional Empty Waveguide Device using traditional of the prior art.

FIG. 2 shows the dimension definition of rectangular Substrate Integrated of the prior art.

FIG. 3 shows a basic empty surface integrated waveguide structure in a PCB published by Belenguer of the prior art.

FIG. 4 shows a microstrip line to empty substrate integrate waveguide (ESIW) connection made in a printed circuit board.

FIG. 5A shows top view, and FIG. 5B an oblique view, of a RF filter that can be a part of the ESIW system of the present invention.

FIG. 6A shows a top view, and FIG. 6B shows an oblique view, of a cavity RF filter that can be a part of the ESIW system of the present invention.

FIG. 7A shows a top view, and FIG. 7B an oblique view, of a RF filter coupler that can be a part of the ESIW system of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

While the making and using of various embodiments of the present invention are discussed in detail below, it should be appreciated that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed herein are merely illustrative of specific ways to make and use the invention and do not delimit the scope of the invention.

To facilitate the understanding of this invention, a number of terms are defined below. Terms defined herein have meanings as commonly understood by a person of ordinary skill in the areas relevant to the present invention. Terms such as “a”, “an” and “the” are not intended to refer to only a singular entity, but include the general class of which a specific example may be used for illustration. The terminology herein is used to describe specific embodiments of the invention, but their usage does not limit the invention, except as outlined in the claims.

The present invention relates in general to the field of glass based empty substrate integrated waveguide devices. More particularly, the present invention relates to the reduction of parasitic capacitance from fringe capacitance in an RF capacitive resonate filter on the same substrate or in a package. In certain aspects, the present invention is a fringe capacitance reduction of a coupled transmission line resonate filters.

Photosensitive glass structures have been suggested for a number of micromachining and microfabrication processes such as integrated electronic elements in conjunction with other elements systems or subsystems. Semiconductor microfabrication using thin film additive processes on semiconductor, insulating or conductive substrates is expensive with low yield and a high variability in performance. An example of additive micro-transmission can be seen in articles Semiconductor Microfabrication Processes by Tian et al., which rely on expensive capital equipment; photolithography and reactive ion etching or ion beam milling tools that generally cost in excess of one million dollars each and require an ultra-clean, high-production silicon fabrication facility costing millions to billions more. This invention provides a cost effective glass ceramic electronic individual device or as an array of passive devices for a uniform response for RF frequencies with low loss, without the need for reactive ion etching or ion beam milling.

The present invention includes a novel method for fabricating a low loss RF empty substrate integrate waveguide (ESIW) structure in APEX Glass structure for use in forming a number of structures with mechanical stabilization and electrical isolation in a photodefinable glass-ceramic. In general, the present invention includes ESIW structure to create in multiple planes of a photodefinable glass-ceramic substrate, such process employing the (a) exposure to excitation energy such that the exposure occurs at various angles by either altering the orientation of the substrate or of the energy source, (b) a bake step and (c) an etch step.

The photosensitive glass substrate can a glass substrate comprising a composition of: 60-76 weight % silica; at least 3 weight % K₂O with 6 weight %-16 weight % of a combination of K₂O and Na₂O; 0.003-1 weight % of at least one oxide selected from the group consisting of Ag₂O and Au₂O; 0.003-2 weight % Cu₂O; 0.75 weight %-7 weight % B₂O₃, and 6-7 weight % Al₂O₃; with the combination of B₂O₃; and Al₂O₃ not exceeding 13 weight %; 8-15 weight % Li₂O; and 0.001-0.1 weight % CeO₂. In another aspect, the photosensitive glass substrate is a glass substrate comprising a composition of: 35-76 weight % silica, 3-16 weight % K₂O, 0.003-1 weight % Ag₂O, 8-15 weight % Li₂O, and 0.001-0.1 weight % CeO₂. In another aspect, the photosensitive glass substrate is at least one of: a photo-definable glass substrate comprises at least 0.1 weight % Sb₂O₃ or As₂O₃, a photo-definable glass substrate comprises 0.003-1 weight % Au₂O; a photo-definable glass substrate comprises 1-18 weight % of an oxide selected from the group consisting of CaO, ZnO, PbO, MgO, SrO and BaO.

The present invention includes a high Q empty substrate integrated waveguide device and/or system with low loss, and that is mechanically and thermally stabilized in a photodefinable glass ceramic substrate. Generally, the ESIW has a Q greater than 20, 30, 35, 36, 37, 38, 39, or 40. In another aspect, the ESIW has a lower cut-off frequency than a printed circuit board waveguide device at the same frequency. In another aspect, the ESIW has a higher peak power handling capability than a printed circuit ESIW.

The present invention has created the capability to create such fabricating a low loss RF ESIW structure including mechanical support elements in both the vertical as well as horizontal plane for photodefinable glass-ceramic substrate.

General Process.

Step 1. Lap and polish a photodefinable glass ceramic substrate or wafer.

Step 2. The photodefinable glass-ceramic substrate is then exposed to the ESIW pattern, ESIW supports and perimeter ground patterns. The ESIW pattern is the basic pattern of the waveguide defining areas of no glass. The ESIW support elements can be a cylindrical pattern can have a diameter ranging from 5 μm to 150 μm in with but preferably 35 μm in diameter. The perimeter ground pattern is the pattern that defines the edges of the waveguide. Patterns are exposed using approximately 20 J/cm² of 310 nm light for 2 to 20 min exposure.

Step 3. Anneal at temperature range heated between of 420° C.-520° C. for between 10 minutes to 2 hours, for the coalescing of silver ions into silver nanoparticles and temperature range heated between 520° C.-620° C. for between 10 minutes and 2 hours allowing the lithium oxide to form around the silver nanoparticles.

Step 4. Coat the topside of the wafer with photoresist; expose and develop a pattern to protect the waveguide pattern while leaving the ground pattern exposed.

Step 5. Spin on blanket photoresist on to the backside of the wafer, place the cooled wafer into an HF bath to etch the exposed ground ceramic portions.

Step 6. Using a standard photoresist stripper, remove the photoresist leaving ground pattern openings and ceramic waveguide areas in the wafer.

Step 7. Place the wafer into a copper electroplating bath and plate the open ground pattern with copper until all ground openings are filled.

Step 8. Coat the backside of the wafer with photoresist; expose and develop a rectangular element with small etch release features, this will become the back side of the ESIW.

Step 9. Using a metallization tool such as a sputtering system deposit 200 Å to 2,000 Å of titanium metal, e.g., 300 Å: followed by a 1 μm deposition of copper onto the backside of the wafer.

Step 10. Using a standard photoresist stripper remove the photoresist leaving rectangular copper element for the bottom of the ESIW structure that is electrically connected to the ground pattern copper.

Step 11. Coat the backside of the wafer with photoresist; expose and develop a rectangular element that is oversized of the ceramic ESIW pattern with etch release features.

Step 12. Place the wafer into a copper electroplating bath and plate the exposed copper areas with between 5-50 um of copper in order to improve the rigidity of the ESIW structure.

Step 13. Using a metallization tool such as a sputtering system deposit 200 Å to 2,000 Å of titanium metal, e.g., 300 Å: followed by a 0.5 um to 1 μm deposition of copper onto the topside of the wafer.

Step 14. Coat the top side of the wafer with photoresist; expose and develop the top side ESIW pattern as well as patterns for RF signal launch elements, Phase matching elements, time delay elements, filter elements and antenna elements.

Step 15. Using a standard photoresist stripper, copper etchant and titanium etchant remove the photoresist and etch any exposed deposition metal, leaving the electroplated copper ESIW patterns.

Step 16. The wafer is then placed into a 0.5% to 50% HF in an ultrasonic bath.

Starting with a photodefinable glass substrate or wafer that is between 1 mm and 250 μm thick lap and polish the photodefinable glass substrate to a root mean square (RMS) surface roughness between 200 Å and 10 Å preferably 50 Å. The photodefinable glass-ceramic substrate is then exposed to the ESIW pattern that includes ESIW supports and perimeter ground patterns. The ESIW pattern is the basic rectangular pattern of the waveguide defining areas. The volume of the rectangular pattern can range between 0% to 100% dielectric. Generally, the volume of the rectangular pattern will have no dielectric material. The ESIW support elements can be a cylindrical pattern, hexagonal or other pattern with a diameter ranging from 5 μm to 200 μm but preferably 35 μm in diameter. The perimeter of the rectangular defines the edges of the waveguide and may be electrically connected to ground. The patterns are exposed using approximately 20 J/cm² of 310 nm light for 2 to 20 min exposure. After exposing the photodefinable glass substrate is annealed at temperature range heated between of 420° C.-520° C. for between 10 minutes to 2 hours. This annealing process coalesces the silver ions into silver nanoparticles. The photodefinable glass substrate is the annealed at a temperature range heated between 520° C.-620° C. for between 10 minutes and 2 hours allowing the lithium oxide to migrate and form around the silver nanoparticles. The top side of the photodefinable glass substrate is then coated with photoresist; where a pattern is exposed and developed to protect the waveguide pattern while leaving the ground pattern exposed. The backside photodefinable glass substrate is coated with a blanket photoresist and then into an HF bath to etch the exposed ground ceramic portions are etched. The HF etchant bath can have a concentration between 2% and 20% but often 10% at room temperature. See FIG. 4 shows an empty substrate integrated waveguide 40 of the present invention. Using a standard photoresist stripper remove the photoresist leaving ground pattern openings and ceramic waveguide areas in the wafer. Place the wafer into a copper electroplating bath and plate the open ground pattern with copper until all ground openings are filled. The copper plating can range from 5 μm to 50 μm bit preferably 20 μm thick. The backside of the photodefinable glass substrate is coated with photoresist. A rectangular element is the exposed and developed including small etch release features. This will become the backside of the ESIW. These etch release features can be rectangular, round or square openings between 10-200 um in size, evenly spaced between 0.05 and 1 mm apart covering the entire ESIW ceramic pattern. Using a metallization tool such as a sputtering system or other metallization tool to deposit 200 Å to 2,000 Å of titanium metal, e.g., 300 Å: followed by a between 0.5 μm to 15 μm, e.g., 1 μm of copper onto the backside of the photodefinable glass substrate. Then using a standard photoresist stripper remove the photoresist leaving rectangular copper element for the bottom of the ESIW structure that is electrically connected to the ground pattern copper. Next, coat the backside of the photodefinable glass substrate with photoresist; expose and develop a rectangular element that is oversized by 5-35% but preferably 15% of the ceramic ESIW pattern with etch release features.

The photodefinable glass substrate is placed into a copper electroplating bath and plate the exposed copper areas with between 5-100 μm of copper in order to improve the rigidity of the ESIW structure. Using a metallization tool such as a sputtering system deposit 200 Å to 2,000 Å of titanium metal preferably 300 Å: followed by a 0.5 μm to 5 μm, e.g., 1 μm deposition of copper onto the topside of the photodefinable glass substrate. The photodefinable glass substrate is then coat the topside with photoresist is exposed and developed with the topside ESIW pattern. This pattern includes patterns for RF signal launch elements, Phase matching elements, time delay elements, filter elements and antenna elements. The photodefinable glass substrate is then placed into a copper electroplating bath and plate the exposed copper areas with between 5-100 μm of copper. The photoresist on the photodefinable glass substrate removed using standard photoresist stripper, copper etchant and titanium etchant remove the photoresist and etch any exposed deposition metal, leaving the electroplated copper ESIW patterns. The photodefinable glass substrate is then placed into a 0.5% to 50% HF solution preferably 10%. The etching process can be accelerated by use of an ultrasonic bath. The ultrasonic bath can be operated in the pulse, sweep and fix mode at frequencies from 28 Khz to 200 Khz to release the ESIW structure and remove all of the defined ceramic structures. The photodefinable glass substrate is then placed into a deionized water (DI) rinse bath to stop the etching process substrate. The photodefinable glass substrate rinsed and dried wafer. The photodefinable glass substrate is then translated to a wafer dicing system to release the ESIW device/system. The ESIW device is a simple antenna combined with an RF signal launch elements. A ESIW system includes phase matching elements, time delay elements, filter elements in addition to antenna and RF signal launch elements.

FIG. 4 shows an empty substrate integrated waveguide 40 of the present invention, in which a substrate 42, in this case the photodefinable glass substrate, has been formed into the device. Integrated with the waveguide 40 are an interconnect area 44 and a waveguide area 45. The edge ground via(s) 48 (EGVs), which are anchor point vias on each side of the removed glass, contact the upper metallization 50 and the lower metallization 52. For the upper metallization 50, the process can be designed to allow for additional circuits or features. Also shown are perforated areas 54 in addition to unsupported metal areas 56, which are not in electrical contact with the edge ground vias 48. A close-up view 58, is shown for the through-vias, that also show the option for cutting-in or undercutting the lower metallization area 52.

FIG. 5A shows top view, and FIG. 5B an oblique view, of a RF filter that can be a part of the ESIW system of the present invention. FIG. 6A shows a top view, and FIG. 6B shows an oblique view, of a cavity RF filter that can be a part of the ESIW system of the present invention. FIG. 7A shows a top view, and FIG. 7B an oblique view, of a RF filter coupler that can be a part of the ESIW system of the present invention. Each of the top and oblique views of 5A to 7B can be used to form the device shown in FIG. 4.

It is contemplated that any embodiment discussed in this specification can be implemented with respect to any method, kit, reagent, or composition of the invention, and vice versa. Furthermore, compositions of the invention can be used to achieve methods of the invention.

It will be understood that particular embodiments described herein are shown by way of illustration and not as limitations of the invention. The principal features of this invention can be employed in various embodiments without departing from the scope of the invention. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, numerous equivalents to the specific procedures described herein. Such equivalents are considered to be within the scope of this invention and are covered by the claims.

All publications and patent applications mentioned in the specification are indicative of the level of skill of those skilled in the art to which this invention pertains. All publications and patent applications are herein incorporated by reference to the same extent as if each individual publication or patent application was specifically and individually indicated to be incorporated by reference.

The use of the word “a” or “an” when used in conjunction with the term “comprising” in the claims and/or the specification may mean “one,” but it is also consistent with the meaning of “one or more,” “at least one,” and “one or more than one.” The use of the term “or” in the claims is used to mean “and/or” unless explicitly indicated to refer to alternatives only or the alternatives are mutually exclusive, although the disclosure supports a definition that refers to only alternatives and “and/or.” Throughout this application, the term “about” is used to indicate that a value includes the inherent variation of error for the device, the method being employed to determine the value, or the variation that exists among the study subjects.

As used in this specification and claim(s), the words “comprising” (and any form of comprising, such as “comprise” and “comprises”), “having” (and any form of having, such as “have” and “has”), “including” (and any form of including, such as “includes” and “include”) or “containing” (and any form of containing, such as “contains” and “contain”) are inclusive or open-ended and do not exclude additional, unrecited elements or method steps. In embodiments of any of the compositions and methods provided herein, “comprising” may be replaced with “consisting essentially of” or “consisting of”. As used herein, the phrase “consisting essentially of” requires the specified integer(s) or steps as well as those that do not materially affect the character or function of the claimed invention. As used herein, the term “consisting” is used to indicate the presence of the recited integer (e.g., a feature, an element, a characteristic, a property, a method/process step or a limitation) or group of integers (e.g., feature(s), element(s), characteristic(s), property(ies), method/process steps or limitation(s)) only.

The term “or combinations thereof” as used herein refers to all permutations and combinations of the listed items preceding the term. For example, “A, B, C, or combinations thereof” is intended to include at least one of: A, B, C, AB, AC, BC, or ABC, and if order is important in a particular context, also BA, CA, CB, CBA, BCA, ACB, BAC, or CAB. Continuing with this example, expressly included are combinations that contain repeats of one or more item or term, such as BB, AAA, AB, BBC, AAABCCCC, CBBAAA, CABABB, and so forth. The skilled artisan will understand that typically there is no limit on the number of items or terms in any combination, unless otherwise apparent from the context.

As used herein, words of approximation such as, without limitation, “about”, “substantial” or “substantially” refers to a condition that when so modified is understood to not necessarily be absolute or perfect but would be considered close enough to those of ordinary skill in the art to warrant designating the condition as being present. The extent to which the description may vary will depend on how great a change can be instituted and still have one of ordinary skill in the art recognize the modified feature as still having the required characteristics and capabilities of the unmodified feature. In general, but subject to the preceding discussion, a numerical value herein that is modified by a word of approximation such as “about” may vary from the stated value by at least ±1, 2, 3, 4, 5, 6, 7, 10, 12 or 15%.

All of the compositions and/or methods disclosed and claimed herein can be made and executed without undue experimentation in light of the present disclosure. While the compositions and methods of this invention have been described in terms of preferred embodiments, it will be apparent to those of skill in the art that variations may be applied to the compositions and/or methods and in the steps or in the sequence of steps of the method described herein without departing from the concept, spirit and scope of the invention. All such similar substitutes and modifications apparent to those skilled in the art are deemed to be within the spirit, scope and concept of the invention as defined by the appended claims.

To aid the Patent Office, and any readers of any patent issued on this application in interpreting the claims appended hereto, applicants wish to note that they do not intend any of the appended claims to invoke paragraph 6 of 35 U.S.C. § 112, U.S.C. § 112 paragraph (f), or equivalent, as it exists on the date of filing hereof unless the words “means for” or “step for” are explicitly used in the particular claim.

For each of the claims, each dependent claim can depend both from the independent claim and from each of the prior dependent claims for each and every claim so long as the prior claim provides a proper antecedent basis for a claim term or element.

It will be understood by those of skill in the art that information and signals may be represented using any of a variety of different technologies and techniques (e.g., data, instructions, commands, information, signals, bits, symbols, and chips may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof). Likewise, the various illustrative logical blocks, modules, circuits, and algorithm steps described herein may be implemented as electronic hardware, computer software, or combinations of both, depending on the application and functionality. Moreover, the various logical blocks, modules, and circuits described herein may be implemented or performed with a general purpose processor (e.g., microprocessor, conventional processor, controller, microcontroller, state machine or combination of computing devices), a digital signal processor (“DSP”), an application specific integrated circuit (“ASIC”), a field programmable gate array (“FPGA”) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Similarly, steps of a method or process described herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

All of the systems, devices, computer programs, compositions and/or methods disclosed and claimed herein can be made and executed without undue experimentation in light of the present disclosure. While the systems, devices, computer programs, compositions and methods of this invention have been described in terms of preferred embodiments, it will be apparent to those of skill in the art that variations may be applied to the systems, devices, computer programs, compositions and/or methods and in the steps or in the sequence of steps of the method described herein without departing from the concept, spirit and scope of the invention. All such similar substitutes and modifications apparent to those skilled in the art are deemed to be within the spirit, scope and concept of the invention as defined by the appended claims.

Claims

1. A method of making an empty substrate integrated waveguide (ESIW) device including antenna and RF signal launch elements comprising the steps of: forming an ESIW pattern, an ESIW supports RF signal launch, a perimeter ground patterns and one or more edges of a waveguide on a wafer comprising lithium ions;annealing the exposed pattern in the presence of silver ions at a temperature that enables silver ions to coalesce into silver nanoparticles, and increasing the temperature to between 520° C.-620° C. to allow lithium oxide to form around the silver nanoparticles;coating a topside of the wafer with a photoresist; exposing and developing a pattern to protect the waveguide pattern while leaving the ground pattern exposed;spinning on a blanket photoresist on a backside of the wafer and etching exposed ground ceramic portions in an HF bath;removing the photoresist leaving one or more ground pattern openings and a ceramic waveguide;electroplating copper on the open ground pattern until all ground openings are filled;coating a backside of the wafer with photoresist; exposing and developing a rectangular element with one or more small etch release features;depositing 200 Å to 2,000 Å of titanium metal to form a first titanium layer, followed by a 1 μm deposition of copper onto the backside of the wafer;removing the photoresist leaving a rectangular copper element to form a bottom of the ESIW structure that is electrically connected to the ground pattern copper and waveguide launching element;exposing and developing a rectangular element in photoresist that is oversized over the ceramic ESIW pattern with the one or more etch release features;electroplating copper on the exposed copper areas with between 5-50 μm of copper to improve the rigidity of the ESIW structure;depositing 200 Å to 2,000 Å of titanium metal to form a second titanium layer followed by a 0.5 um to 1 μm deposition of copper onto the topside of the wafer;coating the top side of the wafer with a photoresist; exposing and developing a top side ESIW pattern;using a standard photoresist stripper, copper etchant and titanium etchant to remove the photoresist and to etch any exposed deposition metal, leaving the electroplated copper ESIW patterns;placing wafer in a 0.5% to 50% HF ultrasonic bath; andwashing the wafer to remove the HF to obtain the empty substrate integrated waveguide device including antenna and RF signal launch elements.

2. The method of claim 1, wherein the ESIW has a Q greater than 40.

3. The method of claim 1, wherein the ESIW has a lower cut-off frequency than a printed circuit board waveguide device at the same frequency.

4. The method of claim 1, wherein the ESIW has a higher peak power handling capability than a printed circuit board waveguide device at the same frequency.

5. The method of claim 1, wherein the first, the second, or both first and second titanium layers have a thickness of 300 Å.

6. A method of creating an empty substrate integrated waveguide system including at least one or more of a phase matching, time delay, crossover or filter elements, connected to an antenna and RF signal launch element, comprising: a. exposing to an ESIW pattern, an ESIW support, RF signal launch, perimeter ground patterns, and the edges of a waveguide;b. annealing the exposed pattern temperature enabling the coalesces silver ions into silver nanoparticles;c. annealing the exposed pattern temperature range heated between 520° C.-620° C. for allowing the lithium oxide to form around the silver nanoparticles;d. coating a topside of the wafer with a photoresist and exposing and developing a pattern to protect the waveguide pattern while leaving the ground pattern exposed;e. spinning on blanket photoresist on to the backside of the wafer and HF bath to etch the exposed ground ceramic portions;f. removing the photoresist to leave ground pattern openings and ceramic waveguide;g. electroplating copper on the open ground pattern until all ground openings are filled;h. coating a backside of the wafer with photoresist; and exposing and developing a rectangular element with one or more small etch release features;i. depositing 200 Å to 2,000 Å of titanium metal to form a first titanium layer followed by a 1 μm deposition of copper onto the backside of the wafer;j. removing the photoresist to leave a rectangular copper element for the bottom of the ESIW structure that is electrically connected to the ground pattern copper and waveguide launching element;k. exposing and developing a rectangular element in photoresist that is oversized of the ceramic ESIW pattern with one or more etch release features;l. Electroplating copper on the exposed copper areas with between 5-50 um of copper in order to improve the rigidity of the ESIW structure;m. depositing 200 Å to 2,000 Å of titanium metal to form a second titanium layer followed by a 0.5 um to 1 μm deposition of copper onto the topside of the wafer;n. coating the top side of the wafer with photoresist; exposing and developing a top side ESIW pattern and patterns for the RF signal launch elements and the antenna elements, and at least one the Phase matching elements, the time delay elements, or the filter elements and;o. using a standard photoresist stripper, copper etchant and titanium etchant to remove the photoresist and to etch any exposed deposition metal, leaving an electroplated copper ESIW patterns;p. placing the wafer into a 0.5% to 50% HF in an ultrasonic bath; andq. washing the wafer to remove the HF.

7. The method of claim 6, wherein the ESIW has a Q greater than 40.

8. The method of claim 6, wherein the ESIW has a lower cut-off frequency than a printed circuit board waveguide device at the same frequency.

9. The method of claim 6, wherein the ESIW has higher peak power handling capability than an ESIW.

10. The method of claim 6, wherein the first, the second, or both first and second titanium layers have a thickness of 300 Å.