The invention generally relates to field of Synchronous Random Access Memories (SRAM) and more particularly to employing write assist.
Submicron SRAM can experience write failures under certain operational conditions. To assist in this regard, “write assist” lines have been developed that pull bitlines below ground to ensure that logical zeros are written in memory cells. However, the circuitry associated with conventional write assist and so-called “negative boost” is costly both in terms of power consumption and area overhead.
SRAM devices herein improve power consumption and area overhead by employing write assist with global bitlines. In these configurations, the write assist line and associated write assist circuitry is eliminated and overall power consumption is reduced by applying a negative boost to local bitlines via the global bitlines. In one embodiment, the SRAM device includes a segmented memory cell array with a plurality of memory cells. Each segment of memory cells includes a bitline coupled to the memory cells in the segment. The SRAM device further includes a global bitline traversing the segmented memory cell array and communicatively coupled to the memory cell segments via the local bitlines for writing to the memory cells. The SRAM device further includes a global input/output module operable to hold the global bitline at logical zero, to toggle the global bitline to logical one when data is to be written, to select one of the segments of memory cells for writing after the global bitline has been toggled, and to toggle the global bitline to logical zero when data is written to the selected memory cell segment to provide a negative boost voltage to the local bitline of the selected memory cell segment.
The various embodiments disclosed herein may be implemented in a variety of ways as a matter of design choice. For example, some embodiments herein are implemented in hardware whereas other embodiments may include processes that are operable to construct and/or operate the hardware. Other exemplary embodiments are described below.
Some embodiments of the present invention are now described, by way of example only, and with reference to the accompanying drawings. The same reference number represents the same element or the same type of element on all drawings.
The figures and the following description illustrate specific exemplary embodiments of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within the scope of the invention. Furthermore, any examples described herein are intended to aid in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited examples and conditions. As a result, the invention is not limited to the specific embodiments or examples described below.
Memory cells (not shown) in the memory array architecture 100 are disposed at intersections of columns and rows. A global Input/Output (I/O) module 102 applies suitable control signals to selected word lines and bitlines to perform a read or write operation for memory cells located at a corresponding row and column. The memory cells may be segmented into multiple banks (e.g., bank 101-1 and 101-2), sometimes referred to as segments, as shown in
Memory cells in each bank 101 are configured in a lower metallization layer (i.e., a first metallization layer or substrate layer of a semiconductor device). Running in each of the banks 101 in column-wise fashion are bitlines 105. A local bitline 105 comprises a true local bitline (BL) 105-1 and a complement local bitline (BLB) 105-2, which are coupled to a corresponding local I/O module 103 and which are specific to a bank 101. The local bitlines 105 in this embodiment are configured in an upper metallization layer (i.e., a second metallization layer above the substrate layer of the semiconductor device).
Global bitlines 104 traverse the banks 101 in column-wise fashion in the upper metallization layer. A global bitline 104 comprises a true global bitline (GBL) 104-1 and a complement global bitline (GBLB) 104-2. Thus, each column of the memory array architecture 100 includes a global bitline 104 associated with multiple banks 101 (e.g., 101-1, 101-2, etc.) and a local bitline 105 specific to each bank 101. Both the global bitlines 104 and the local bitlines 104 run in the upper metallization layer. The global bitlines 104 are toggled by the global I/O module 102 and couple to the banks 101 via the local bitlines 105, thereby allowing write operations to be performed on memory cells.
The coupling that occurs between the global bitlines 104 and the local bitlines 105 in the upper metallization layer allows the global I/O module 102 to direct an appropriate negative boost to the local bitline 105 to assist in a write operation to a memory cell. Thus, global bitline 104 is used both for carrying data and for providing write assist via direct coupling with the local bitline 104. This eliminates the associated write assist circuitry that would normally be needed to provide a negative boost on the local bitline 105.
Discussion of the operation of the global I/O module 102 will now be directed to the flowchart of
As mentioned, the circuitry of
As an example, true global bitline 104-1 may be pulled high, which then transfers data onto its corresponding true local bitline 105-1 in a selected bank 101 by pulling the true local bitline 105-1 to logical zero. When the true local bitline 105-1 reaches logical zero, the true global bitline 104-1 is pulled low. Because of the coupling between the true global bitline 104-1 and the true local bitline 105-1, when the true global bitline 104-1 is pulled low it invokes a negative boost on the true local bitline 105-1 which assists in writing to a memory cell in the selected bank 101.
Thus, a negative boost on the local bitline 105 is provided without using a write assist line. And, the high to low transition of the global bitline 104 that provides the negative boost to the corresponding local bitline 105 does not consume any extra power since the global bitlines 104 are pulled low at the end of a write cycle anyway. Also, leakage in the global bitlines 104 is reduced since they are held at logical zero by default. The coupling between the global bitlines 104 and the local bitlines 105 also enables a relatively constant amount of negative boost throughout a range of rows of the memory cell architecture 100.
The bank 101 is selected by the global I/O module 102 by toggling the bank select signal 108 to logical one. Before a write operation of a particular memory cell, the precharge signal 110 may enable precharging of the local bitlines 105 to a known voltage such as voltage rail or supply voltage.
It will be appreciated that the terms upper, lower, first, second, and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular orientation or order. In other words, the terms so used are interchangeable under appropriate circumstances and the embodiments of the disclosure herein can operate in orientations and sequences other than that which is described or illustrated herein. Additionally, those skilled in the art will understand that the embodiments discloses herein may be applicable to a number of different multi-bank and split bitline architectures.
This patent application claims priority to, and thus the benefit of an earlier filing date from, U.S. Provisional Patent Application No. 61/905,547 (filed Nov. 18, 2013), the entire contents of which are hereby incorporated by reference.
Number | Date | Country | |
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61905547 | Nov 2013 | US |