Patent Application
20090321809
The disclosure relates to the field of semiconductor manufacturing. In particular, the disclosure relates to tunnel barrier engineering in memory devices.
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of claimed subject matter. However, it will be understood by those skilled in the art that claimed subject matter may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure claimed subject matter.
NAND flash device 100 may comprise substrate 120 having source 104, drain 106, P-well 108, deep N-well 110, and P-substrate 112 formed therein. According to a particular embodiment, substrate 120 may comprise a variety of materials such as silicon, gallium arsenide, silicon carbide, silicon germanium, germanium and/or polysilicon and claimed subject matter is not limited in this regard.
In a particular embodiment, NAND flash device 100 may additionally comprise floating gate 114 and control gate 116. According to a particular embodiment, device 100 may comprise layer 118 formed between floating gate 114 and control gate 116. Layer 118 may comprise a variety of materials, such as, for instance, oxide-nitride-oxide (ONO), hafnium oxide (HfOx), aluminum oxide (AlOx), zirconium oxide (ZrOx), zirconium aluminum oxide (ZrAlOx), hafnium aluminum oxide (HfAlOx) or hafnium oxide-aluminum oxide-hafnium oxide (HfOx-AlOx-HfOx), or combinations of these films and/or multi-layers incorporating these films. Floating gate 114 and control gate 116 may comprise any of a variety of materials known to those skilled in the art and may be formed by any of a variety of methods known to those skilled in the art and claimed subject matter is not limited in this regard.
According to a particular embodiment, NAND flash device 100 may further comprise tunnel barrier 102 formed between substrate 120 and floating gate 114. According to a particular embodiment, tunnel barrier 102 may comprise first barrier layer 122, graded oxy-nitride layer 124 and second barrier layer 126. Tunnel barrier 102 may provide charge transport for either through tunneling or hot carrier injection. According to a particular embodiment, graded oxy-nitride layer 124 may comprise a nitrogen gradient extending between first barrier layer 122 and second barrier layer 126 as is explained in greater detail with respect to
In a particular embodiment, graded oxy-nitride layer 124 may be formed by nitriding portion 131 of foundation layer 129 from plane 130 to plane 128 thus forming first barrier layer 122 and graded oxy-nitride layer 124. Controlling nitriding conditions may enable forming a nitrogen gradient in oxy-nitride layer 124 having a concentration that generally increases from plane 128 to plane 130. Wherein the area of lowest concentration of nitrogen may be at or near plane 128 and may vary over graded oxy-nitride layer 124 to an area of greatest nitrogen concentration at or near plane 130. Formation of graded oxy-nitride layer 124 within foundation layer 129 may enable formation of foundation layer 129 to greater thicknesses than in conventional methods thus enabling improved control of the thickness of first barrier layer 122.
As is shown in
In a particular embodiment, where graded oxy-nitride layer 124 is formed by decoupled plasma nitridation (DPN) of foundation layer 129 at plane 130 and where foundation layer 129 comprises silicon dioxide (SiO2), DPN at plane 130 may form an oxy-nitride layer 124 comprising silicon oxy-nitride (SiON) having a nitrogen concentration gradient. However this is merely an example of an oxy-nitride layer that may be formed by DPN where a foundation layer comprises SiO2 and claimed subject matter is not limited in this regard.
According to a particular embodiment, nitrogen may be incorporated to a depth D 132 into foundation layer 129 to form oxy-nitride layer 124. Depth D 132 may be about 1 to 50 Å as measured from plane 130. However, this is merely an example of a method of forming a graded oxy-nitride layer to a particular depth and claimed subject matter is not limited in this regard.
In a particular embodiment, a concentration of nitrogen may be varied from 0-80 atomic percent as measured over depth D 132 of oxy-nitride layer 124. In a particular embodiment, such a nitrogen gradient may begin at a depth of between about 1 to 50 Å below plane 130. Such a nitrogen concentration may generally increase from plane 128 to plane 130. However, this is merely an example of a particular embodiment of a nitrogen gradient of a graded oxy-nitride layer and claimed subject matter is not limited in this regard.
According to a particular embodiment, second barrier layer 126 may be formed over graded nitride layer 124. In a particular embodiment, second barrier layer 126 may be formed by a variety of methods known to those skilled in the art (for example, various deposition techniques and/or growth techniques may be used). Second barrier layer 126 may comprise a variety of materials such as silicon nitride and/or silicon dioxide and claimed subject matter is not limited in this regard. In a particular embodiment, second layer 126 may also be formed by depositing a silicon nitride layer and subsequent conversion of silicon nitride to silicon dioxide by oxidation.
According to a particular embodiment, NAND flash device 300 may comprise a variety of materials such as a metal-insulator-nitride-oxide-silicon MINOS system and claimed subject matter is not limited in this regard. In a particular embodiment, charge trapping layer 314 may comprise a variety of materials, such as, for instance, a variety of high-k dielectrics, nano-dot material, nitride, silicon nitride, hafnium oxide (HfOx), aluminum oxide (AlOx), zirconium oxide (ZrOx), zirconium aluminum oxide (ZrAlOx), hafnium aluminum oxide (HfAlOx), lanthanum oxide (LaOx) or hafnium oxide-aluminum oxide-hafnium oxide (HfOx-AlOx-HfOx), or combinations thereof. Additionally, NAND flash device 300 may comprise substrate 320 having source 304, drain 306 and P-well 308 formed therein. In a particular embodiment, NAND flash device 300 may additionally comprise blocking oxide 318 and control gate 316. However, this is merely an example of an embodiment of a NAND flash device assembly comprising a charge trapping layer and claimed subject matter is not limited in this regard.
According to a particular embodiment, device 300 may further comprise tunnel barrier layer 302 formed between substrate 320 and charge trapping layer 314. According to a particular embodiment, tunnel barrier 302 may comprise first barrier layer 322, graded oxy-nitride layer 324 and second barrier layer 326. According to a particular embodiment, graded oxy-nitride layer 324 may comprise a nitride gradient extending between first barrier layer 322 and second barrier layer 326.
In a particular embodiment, process 400 may flow to block 404 where a graded nitride layer may be formed in a foundation layer by nitriding a surface of the foundation layer. As previously discussed, graded nitride layer 124 may be formed by various methods such as DPN and/or annealing in ambient of ammonia (NH3), nitrogen (N2), nitric oxide (NO) and/or nitrous oxide (N2O). Such nitriding may form a graded oxy-nitride layer within a portion of previously formed foundation layer converting the foundation layer to a first barrier layer and an oxy-nitride layer.
In a particular embodiment, where a foundation layer comprises SiO2 a graded oxy-nitride layer as formed in a foundation layer may comprise silicon oxy-nitride (SiON). In other particular embodiments, where a foundation layer may comprise; aluminum oxide (AlOx), hafnium silicon oxide (HfSiOx), aluminum silicon oxide (AlSiOx), zirconium oxide (ZrOx) and/or zirconium silicon oxide (ZrSiOx) a graded oxy-nitride layer may comprise; silicon oxy-nitride (SiON), aluminum oxy-nitride (AlON), hafnium silicon oxy-nitride (HfSiON), aluminum silicon oxy-nitride (AlSiON), zirconium oxy-nitride (ZrON) and/or zirconium silicon oxy-nitride (ZrSiON), respectively and claimed subject matter is not limited in this regard.
In a particular embodiment, at block 404 a graded oxy-nitride layer may be formed such that nitrogen may be incorporated to a depth of about 1 Å to 50 Å from a surface of a foundation layer (see foundation layer 129 and depth indicator 132 of
Table 1 below provides example DPN powers and times and average nitrogen concentrations of an oxy-nitride layer for a number of samples to show how nitrogen concentration may be a function of DPN power and time.
Referring again to
In a particular embodiment, process 400 may flow to block 408 where a second barrier layer anneal may occur. Such a second barrier layer anneal may be performed by a variety of methods such as a high temperature and/or nitrogen or oxygen anneal to heal defects in the second layer and improve the quality of the second barrier layer oxide.
Graph 600 shows the variation in nitrogen concentration with respect to depth as measured through a thickness of oxy-nitride layer 124 (as shown in
While certain features of claimed subject matter have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such embodiments and changes as fall within the spirit of claimed subject matter.
