Claims
- 1. A computer system comprising:
- a central processing unit (CPU) for processing data;
- a memory for storing data;
- means including a predetermined input device for transferring data to said memory;
- means including a system control processor (SCP adapted to be electrically connected to said transferring means for monitoring said transferring means, said SCP being incompatible with a predetermined SCP interface; and
- means for interfacing said SCP to said CPU, said interfacing means being disposed between said CPU and said SCP, said interfacing means including a first means for enabling said CPU to communicate with said SCP, said first means writable by said CPU and readable by said SCP, second means for enabling said SCP to communicate with said CPU, said second means readable by said CPU and readable and writable by said SCP, and means for controlling communications with said first and said second enabling means, said communications controlling means providing status information to be read by said SCP before said SCP writes to said second enabling means, said interfacing means further including means for hardware emulation of said predetermined SCP interface.
- 2. A computer system as recited in claim 1 wherein said interfacing means includes means for generating a predetermined signal to enable the CPU to access memory above one megabyte.
- 3. A computer system as recited in claim 2, wherein said generating means includes first allowing means for allowing said CPU to initiate the generation of said predetermined signal.
- 4. A computer system as recited in claim 2, wherein said generating means includes second allowing means for allowing said SCP to initiate generation of said predetermined signal.
- 5. A computer system as recited in claim 5 wherein said SCP is an Intel type 8051 processor.
- 6. A computer system as recited in claim 1, wherein said first enabling means is an input buffer, said second enabling means is an output buffer, and said communications controlling means is a status register.
- 7. A computer system as recited in claim 1, wherein said predetermined system control processor interface is compatible with an Intel type 8042 processor.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is a continuation of U.S. patent application Ser. No. 08/336,570, filed Nov. 9, 1994, now abandoned, entitled FAST SWITCHING MEMORY MODE SYSTEM, which is a divisional of U.S. patent application Ser. No. 08/139,946, now abandoned, filed Dec. 8, 1993, entitled FAST SWITCHING MEMORY MODE SYSTEM, which is a continuation of Ser. No. 08/031,029, now U.S. Pat. No. 5,283,889 reissued as U.S. Pat. No. RE35480, entitled HARDWARE BASED INTERFACE FOR MODE SWITCHING TO ACCESS MEMORY ABOVE ONE MEGABYTE which is a continuation of U.S. patent application Ser. No. 07/735,619, filed Jul. 25, 1991, now abandoned, entitled FAST SWITCHING MEMORY MODE SYSTEM, which is a continuation-in-part of U.S. patent application Ser. No. 07/459,055, filed Dec. 29, 1989, now abandoned, entitled FAST SWITCHING MEMORY MODE SYSTEM.
US Referenced Citations (12)
Divisions (1)
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Date |
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139946 |
Dec 1993 |
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Continuations (3)
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Number |
Date |
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336570 |
Nov 1994 |
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Parent |
31029 |
Mar 1993 |
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Parent |
735619 |
Jul 1991 |
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Continuation in Parts (1)
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459055 |
Dec 1989 |
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