Patent Application
20170329607
The field of the invention is data processing, or, more specifically, methods, apparatus, and products for hazard avoidance in a multi-slice processor.
The development of the EDVAC computer system of 1948 is often cited as the beginning of the computer era. Since that time, computer systems have evolved into extremely complicated devices. Today's computers are much more sophisticated than early systems such as the EDVAC. Computer systems typically include a combination of hardware and software components, application programs, operating systems, processors, buses, memory, input/output devices, and so on. As advances in semiconductor processing and computer architecture push the performance of the computer higher and higher, more sophisticated computer software has evolved to take advantage of the higher performance of the hardware, resulting in computer systems today that are much more powerful than just a few years ago.
One area of computer system technology that has advanced is computer processors. As the number of computer systems in data centers and the number of mobile computing devices has increased, the need for more efficient computer processors has also increased. Speed of operation and power consumption are just two areas of computer processor technology that affect efficiency of computer processors.
Methods and apparatus for hazard avoidance in a multi-slice processor are disclosed in this specification. Hazard avoidance in a multi-slice processor includes adding, to a hazard table, an entry for an effective address, wherein the entry comprises an instruction tag (ITAG) offset for the effective address; fetching, by an instruction fetch unit, a processor instruction from a memory location using the effective address; determining that the hazard table includes the entry for the effective address; retrieving, from the hazard table, the ITAG offset for the effective address; identifying a prior internal operation (TOP) using the ITAG offset; and decoding the processor instruction into a load IOP with a dependency on the prior IOP.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts of exemplary embodiments of the invention.
Exemplary methods and apparatus for hazard avoidance in a multi-slice processor in accordance with the present invention are described with reference to the accompanying drawings, beginning with
The computer (152) of
The example computer processor (156) of
The example multi-slice processor (156) of
Although the multi-slice processor (156) in the example of
Stored in RAM (168) in the example computer (152) is a data processing application (102), a module of computer program instructions that when executed by the multi-slice processor (156) may provide any number of data processing tasks. Examples of such data processing applications may include a word processing application, a spreadsheet application, a database management application, a media library application, a web server application, and so on as will occur to readers of skill in the art. Also stored in RAM (168) is an operating system (154). Operating systems useful in computers configured for operation of a multi-slice processor according to embodiments of the present invention include UNIX™, Linux™, Microsoft Windows™, AIX™, IBM's z/OS™, and others as will occur to those of skill in the art. The operating system (154) and data processing application (102) in the example of
The computer (152) of
The example computer (152) of
The exemplary computer (152) of
The arrangement of computers and other devices making up the exemplary system illustrated in
For further explanation,
The multi-slice processor in the example of
The general purpose registers (206) are configured to store the youngest instruction targeting a particular logical register and the result of the execution of the instruction. A logical register is an abstraction of a physical register that enables out-of-order execution of instructions that target the same physical register.
When a younger instruction targeting the same particular logical register is received, the entry in the general purpose register is moved to the history buffer, and the entry in the general purpose register is replaced by the younger instruction. The history buffer (208) may be configured to store many instructions targeting the same logical register. That is, the general purpose register is generally configured to store a single, youngest instruction for each logical register while the history buffer may store many, non-youngest instructions for each logical register.
Each execution slice (204) of the multi-slice processor of
The arithmetic logic unit (212) depicted in the example of
The results bus (220) may be configured in a variety of manners and be of composed in a variety of sizes. In some instances, each execution slice may be configured to provide results on a single bus line of the results bus (220). In a similar manner, each load/store slice may be configured to provide results on a single bus line of the results bus (220). In such a configuration, a multi-slice processor with four processor slices may have a results bus with eight bus lines—four bus lines assigned to each of the four load/store slices and four bus lines assigned to each of the four execution slices. Each of the execution slices may be configured to snoop results on any of the bus lines of the results bus. In some embodiments, any instruction may be dispatched to a particular execution unit and then by issued to any other slice for performance. As such, any of the execution slices may be coupled to all of the bus lines to receive results from any other slice. Further, each load/store slice may be coupled to each bus line in order to receive an issue load/store instruction from any of the execution slices. Readers of skill in the art will recognize that many different configurations of the results bus may be implemented.
The multi-slice processor in the example of
The example multi-slice processor of
During the flush and recovery operation, in prior art processors, the dispatcher was configured to halt dispatch of new instructions to an execution slice. Such instructions may be considered either target or source instructions. A target instruction is an instruction that targets a logical register for storage of result data. A source instruction by contrast has, as its source, a logical register. A target instruction, when executed, will result in data stored in an entry of a register file while a source instruction utilizes such data as a source for executing the instruction. A source instruction, while utilizing one logical register as its source, may also target another logical register for storage of the results of instruction. That is, with respect to one logical register, an instruction may be considered a source instruction and with respect to another logical register, the same instruction may be considered a target instruction.
The multi-slice processor in the example of
In some cases, a load/store unit receiving an issued instruction, such as a load/store slice, may not yet be able to handle the instruction, and the instruction sequencing unit (240) may keep the instruction queued until such time as the load/store slice may handle the instruction. After the instruction is issued, the instruction sequencing unit (240) may track progress of the instruction based at least in part on signals received from a load/store slice.
For further explanation,
The instruction fetch unit (300) also includes branch prediction logic (310). Branch prediction logic generally performs branch prediction for pre-decoded instructions and tracks various branch prediction statistics for executing and executed instructions. The branch prediction logic (310) may include or access various registers and storage that contain such branch prediction statistics. Examples of storage entities may include global branch history tables and the like.
The instruction fetch unit (300) also includes an instruction fetch logic (306). The instruction fetch logic (306) generally retrieves instructions from the instruction cache and provides the fetched instruction to instruction decode logic (308).
The example instruction decode logic (308) of
For further explanation,
The hazard table is a data structure implemented to avoid flushes caused by certain hazards, such as store-hit-load hazards. A store-hit-load hazard may occur in an out-of-order processing system when a load internal instruction (IOP) reads from a location in cache or from memory before the expected result data has been stored in that location. Once the hazard has been detected, a flush is initiated of the load instruction or all instructions after the store. The flush may cause the flushed instructions to be refetched by the instruction fetch unit. If the same set of instructions, including the load and store, are executed multiple times by the multi-slice processor, the same hazard may occur (and therefore the flush) each time the instructions are executed.
The hazard table enables the instruction fetch unit (300) to create a dependency tracked by the other elements in the multi-slice processor. This dependency informs those elements, such as the load store unit (222), that the load IOP should not be executed until the execution of the store IOP has completed. The hazard table may be stored in the instruction fetch unit and implemented in a variety of data structures. For example, the hazard table may be a direct lookup table, a hash table, an array, or any other type of data structure that provides one value keyed to another value.
An ITAG is an instruction identifier. Each ITAG tracks an internal operation from decode to completion. Each internal operation may be assigned an ITAG by an ITAG assignment unit, which assigns ITAGs sequentially to internal operations (IOPs) before the internal operations are transmitted to a dispatch unit. IOPs are the result of decoding processor instructions, and each IOP is tracked using an ITAG. Processor instructions may be decoded into a single IOP or may be decoded into a plurality of IOPs.
The ITAG offset is an indicator of the prior IOP that the load IOP decoded from the instruction stored at the effective address should be made dependent upon. The ITAG offset may be a value that separates the ITAG for a load IOP and the ITAG for a store ITAG upon which the load ITAG is to be made dependent. For example, if the ITAG for a load IOP is “24” and the ITAG for a store IOP is “14”, then the ITAG offset may be “10”. The ITAG offset may include the ITAG of the prior IOP itself. For example, if the ITAG for a load IOP is “24” and the ITAG for a store IOP is “14”, then the ITAG offset may be “14” (the value of the ITAG for the store IOP).
The method of
The method of
The method of
The method of
The prior IOP may be a store IOP that stores result data into memory read by the load IOP. For example, a load IOP may read result data from memory (such as L1 cache) placed in memory by a store IOP. The load IOP and store IOP may be part of a set of processor instructions that are executed multiple times. Further, the conditions under which the load IOP and store IOP are executed may cause the load IOP to read the memory before the store IOP has stored the result data in the memory (triggering the hazard and resulting in a flush). The prior IOP may be a store IOP whose delay against the load IOP causes the hazard.
Identifying (410) a prior IOP using the ITAG offset may not necessary identify the intended IOP. For example, the prior IOP may be intended to be a store IOP that stores result data in memory read by a load IOP decoded from the processor instruction. However, the calculations or processing of the ITAG offset may result in an ITAG value that is not the ITAG value that has been assigned to the store IOP (such as an IOP decoded before or after the store IOP). This may occur, for example, if one or more conditional branches were taken between the store TOP and the load TOP because of a different conditional outcome. This would cause the processor instructions that include the store and load to be refetched in a different order, and be assigned ITAGs with a different offset in subsequent decodings.
The method of
The processor instruction may be decoded into multiple IOPs. In order to determine which of the decoded IOPs is the load TOP, the instruction fetch unit (300) may have knowledge of which of the decoded IOPs is the load TOP. This may be in the form of a table stored in the instruction fetch unit that informs the instruction decode logic (308) regarding which of the IOPs decoded is the load TOP. Alternatively, the instruction fetch unit (300) may assign the dependency to each decoded TOP.
The dependency on the prior TOP may be tracked using an ITAG for the load TOP and an ITAG for the prior TOP. For example, the issue queue of the load store slice (222) may include a field for the ITAG of IOPs upon which a store TOP is dependent. The load store slice (222) may then wait until the result data from the TOP associated with the ITAG is available before executing the load TOP stored in the issue queue.
As discussed above, the identified prior TOP may not be the store TOP that stores result data in memory read by a load TOP. If another TOP is identified, then the load TOP may be made dependent upon an TOP that may not be directly related to the execution of the load TOP. However, this may still provide a beneficial result, in that the load TOP may be delayed sufficiently by having to wait on the prior TOP that the store TOP is provided enough time to complete. Further, the store TOP may have already been executed before the load TOP is dispatched. Therefore, the instruction sequencer unit (240) may be configured to determine that the dependency has been met once the load TOP has been received.
For further explanation,
The method of
Receiving (502) a flush indication comprising a flush ITAG and the ITAG offset may be carried out by a load store slice (222) detecting a hazard and flushing the hazard-causing TOP. The load store slice (222) may then notify the instruction fetch unit (300) of the flush and include the ITAG of the flushed TOP along with the ITAG offset (indicating the ITAG of the TOP whose delay triggered the flush).
The flush ITAG may identify a prior load TOP previously decoded from the processor instruction. Specifically, the same group of processor instructions may be fetched and executed multiple times in the course of executing code. Accordingly, the same processor instruction may be fetched and decoded multiple times. The flush ITAG may therefore be the ITAG previously assigned to a load TOP previously decoded from the processor instruction.
The ITAG offset may be transmitted from a load store slice (222) instead of the ITAG of the store TOP in order to reduce the size of the flush indication. For example, an ITAG may require 9 bits and an ITAG offset may require 6 bits. It would therefore be more efficient to transmit the ITAG offset and the ITAG of the load IOP instead of the ITAG for the store IOP and the ITAG for the load IOP.
Obtaining (504) the effective address using the flush ITAG may be carried out using an effective address table (EAT) and a processor instruction vector. The flush ITAG may be compared to rows of the EAT to determine an EAT row that includes the flush ITAG. The EAT row includes a range of effective addresses and the first ITAG assigned to the IOPs decoded from the range of effective addresses. The number of ITAGs assigned to the effective address range may be obtained using the processor instruction vector, and an effective address offset may be derived from the flush ITAG and the processor instruction vector. Finally, the effective address offset may be applied to the effective address range in the effective address row to obtain the effective address of the processor instruction for the flush ITAG.
The load store slice (222) may flush all IOPs after the store IOP or may just flush the IOPs after (and including) the load IOP that triggered the flush. If all IOPs following the store IOP are flushed, then the instruction fetch unit (300) may obtain the effective address of both the ITAG of the IOP following the store IOP and the ITAG of the load IOP. The effective address of the ITAG for the IOP following the store IOP is used to start refetching the instructions following the flush. The effective address of the ITAG for the load IOP (i.e., the flush ITAG) may be used to create the entry in the hazard table.
Storing (506) the ITAG offset keyed to the effective address in the hazard table may be carried out by creating an entry in the hazard table using the effective address as a key, and storing the ITAG offset in the entry.
For further explanation,
The method of
For further explanation,
The method of
Storing (704) the dependency on the prior TOP with the load TOP in the load store slice (222) may be carried out by storing the ITAG of the prior TOP with the load TOP and the ITAG of the load TOP in an issue queue of the load store slice (222).
The load store slice (222) may wait until the result data has been stored in memory before executing the load TOP. Specifically, the load store slice (222) may read the ITAG of the prior TOP and place the load TOP in a wait state until the result data stored by the store TOP is available or expected to be available.
Exemplary embodiments of the present invention are described largely in the context of a fully functional computer system for hazard avoidance in a multi-slice processor. Readers of skill in the art will recognize, however, that the present invention also may be embodied in a computer program product disposed upon computer readable storage media for use with any suitable data processing system. Such computer readable storage media may be any storage medium for machine-readable information, including magnetic media, optical media, or other suitable media. Examples of such media include magnetic disks in hard drives or diskettes, compact disks for optical drives, magnetic tape, and others as will occur to those of skill in the art. Persons skilled in the art will immediately recognize that any computer system having suitable programming means will be capable of executing the steps of the method of the invention as embodied in a computer program product. Persons skilled in the art will recognize also that, although some of the exemplary embodiments described in this specification are oriented to software installed and executing on computer hardware, nevertheless, alternative embodiments implemented as firmware or as hardware are well within the scope of the present invention.
The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.
The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.
Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.
These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
It will be understood from the foregoing description that modifications and changes may be made in various embodiments of the present invention without departing from its true spirit. The descriptions in this specification are for purposes of illustration only and are not to be construed in a limiting sense. The scope of the present invention is limited only by the language of the following claims.
